9d6cd3d858
This commit adds drivers for Alpine Cache Coherency Unit and North Bridge Service whose task is to configure the system fabric and enable cache coherency. Obtained from: Semihalf Submitted by: Michal Stanek <mst@semihalf.com> Sponsored by: Annapurna Labs Reviewed by: wma Differential Revision: https://reviews.freebsd.org/D7565
251 lines
7.0 KiB
Plaintext
251 lines
7.0 KiB
Plaintext
/*-
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* Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
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* Copyright (c) 2015 Semihalf
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/dts-v1/;
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/ {
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model = "annapurna,alpine";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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serial0 = &serial0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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d-cache-line-size = <64>; // 64 bytes
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i-cache-line-size = <64>; // 64 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <0>;
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bus-frequency = <375000000>;
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clock-frequency = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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d-cache-line-size = <64>; // 64 bytes
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i-cache-line-size = <64>; // 64 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <0>;
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bus-frequency = <375000000>;
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clock-frequency = <0>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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d-cache-line-size = <64>; // 64 bytes
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i-cache-line-size = <64>; // 64 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <0>;
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bus-frequency = <375000000>;
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clock-frequency = <0>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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d-cache-line-size = <64>; // 64 bytes
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i-cache-line-size = <64>; // 64 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <0>;
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bus-frequency = <375000000>;
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clock-frequency = <0>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00100000 0x7ff00000>; // 2047MB at 1MB
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x0 0xfb000000 0x03000000>;
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bus-frequency = <0>;
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MPIC: interrupt-controller {
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compatible = "arm,gic";
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reg = < 0x1000 0x1000 >, /* Distributor Registers */
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< 0x2000 0x2000 >; /* CPU Interface Registers */
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <3>;
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// In intr[2], bits[3:0] are trigger type and level flags.
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// 1 = low-to-high edge triggered
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// 2 = high-to-low edge triggered
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// 4 = active high level-sensitive
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// 8 = active low level-sensitive
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// The hardware only supports active-high-level or rising-edge.
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};
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generic_timer {
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compatible = "arm,sp804";
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reg = <0x02890000 0x1000>;
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interrupts = <0 9 4>;
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interrupt-parent = <&MPIC>;
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clock-frequency = <375000000>;
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};
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cpu_resume {
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compatible = "annapurna-labs,al-cpu-resume";
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reg = <0x00ff5ec0 0x30>;
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};
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ccu {
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compatible = "annapurna-labs,al-ccu";
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reg = <0x00090000 0x10000>;
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io_coherency = <1>;
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};
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nb_service {
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compatible = "annapurna-labs,al-nb-service";
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reg = <0x00070000 0x10000>;
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interrupts = <0 32 4>,
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<0 33 4>,
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<0 34 4>,
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<0 35 4>;
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interrupt-parent = <&MPIC>;
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};
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wdt0 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x288c000 0x1000>;
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interrupt-parent = <&MPIC>;
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};
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serial0: serial@2883000 {
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compatible = "ns16550";
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reg = <0x2883000 0x20>;
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reg-shift = <2>;
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current-speed = <115200>;
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clock-frequency = <375000000>;
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interrupts = <0 17 4>;
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interrupt-parent = <&MPIC>;
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};
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};
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pcie-internal {
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compatible = "annapurna-labs,al-internal-pcie";
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device_type = "pci";
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#size-cells = <2>;
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#address-cells = <3>;
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interrupt-parent = <&MPIC>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <0x3000 0 0 1 &MPIC 0 32 4>, // USB adapter
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<0x3800 0 0 1 &MPIC 0 36 4>,
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<0x4000 0 0 1 &MPIC 0 43 4>, // SATA 0 (PCIe expander)
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<0x4800 0 0 1 &MPIC 0 44 1>; // SATA 1 (onboard)
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// ranges:
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// - ECAM - non prefetchable config space
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// - 32 bit non prefetchable memory space
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ranges = <0x00000000 0x0 0xfbc00000 0xfbc00000 0x0 0x100000
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0x02000000 0x0 0xfe000000 0xfe000000 0x0 0x1000000>;
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bus-range = <0x00 0x00>;
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};
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// WORKAROUND: enabling PCIe controller when no card is plugged in
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// leads to kernel panic because u-boot disables PCIe controller if no link
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// is detected. Just be kind and compatible with Linux
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/* // External PCIe Controller 0
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pcie-external0 {
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compatible = "annapurna-labs,al-external-pcie";
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reg = <0xfd800000 0x00020000>;
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device_type = "pci";
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#size-cells = <2>;
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#address-cells = <3>;
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interrupt-parent = <&MPIC>;
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interrupt-map-mask = <0x00 0 0 7>;
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interrupt-map = <0x0000 0 0 1 &MPIC 0 40 4>;
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// ranges:
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// Controller 0:
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// - ECAM - non prefetchable config space: 2MB
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// - IO - IO port space 64KB, reserve 64KB from target memory windows
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// real IO address on the pci bus starts at 0x10000
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// - 32 bit non prefetchable memory space: 128MB - 64KB
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ranges = <0x00000000 0x0 0xfb600000 0xfb600000 0x0 0x00200000
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0x01000000 0x0 0x00010000 0xe0000000 0x0 0x00010000
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0x02000000 0x0 0xe1000000 0xe1000000 0x0 0x06f00000>;
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bus-range = <0x00 0xff>;
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};
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// External PCIe Controllers 1
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pcie-external1 {
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compatible = "annapurna-labs,al-external-pcie";
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reg = <0xfd820000 0x00020000>;
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device_type = "pci";
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#size-cells = <2>;
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#address-cells = <3>;
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interrupt-parent = <&MPIC>;
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interrupt-map-mask = <0x0 0 0 7>;
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interrupt-map = <0x0000 0 0 1 &MPIC 0 41 4>;
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// ranges:
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// - ECAM - non prefetchable config space: 2MB
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// - IO - IO port space 64KB, reserve 64KB from target memory windows
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// real IO address on the pci bus starts at 0x20000
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// - 32 bit non prefetchable memory space: 64MB - 64KB
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ranges = <0x00000000 0x0 0xfb800000 0xfb800000 0x0 0x00200000
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0x01000000 0x0 0x00020000 0xe8000000 0x0 0x00010000
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0x02000000 0x0 0xe8100000 0xe8100000 0x0 0x02ff0000>;
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bus-range = <0x00 0xff>;
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}; */
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chosen {
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stdin = "serial0";
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stdout = "serial0";
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stddbg = "serial0";
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};
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};
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