af3dc4a7ca
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
763 lines
22 KiB
C
763 lines
22 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
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* Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/gpio.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <sys/taskqueue.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/intr.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/mmc/bridge.h>
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#include <dev/mmc/mmcreg.h>
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#include <dev/mmc/mmcbrvar.h>
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#include <dev/sdhci/sdhci.h>
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#include <dev/sdhci/sdhci_fdt_gpio.h>
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#include "sdhci_if.h"
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#include <arm/ti/ti_cpuid.h>
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#include <arm/ti/ti_prcm.h>
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#include <arm/ti/ti_hwmods.h>
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#include "gpio_if.h"
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#include "opt_mmccam.h"
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struct ti_sdhci_softc {
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device_t dev;
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struct sdhci_fdt_gpio * gpio;
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struct resource * mem_res;
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struct resource * irq_res;
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void * intr_cookie;
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struct sdhci_slot slot;
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clk_ident_t mmchs_clk_id;
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uint32_t mmchs_reg_off;
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uint32_t sdhci_reg_off;
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uint32_t baseclk_hz;
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uint32_t cmd_and_mode;
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uint32_t sdhci_clkdiv;
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boolean_t disable_highspeed;
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boolean_t force_card_present;
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boolean_t disable_readonly;
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};
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/*
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* Table of supported FDT compat strings.
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*
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* Note that "ti,mmchs" is our own invention, and should be phased out in favor
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* of the documented names.
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*
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* Note that vendor Beaglebone dtsi files use "ti,omap3-hsmmc" for the am335x.
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*/
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static struct ofw_compat_data compat_data[] = {
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{"ti,omap3-hsmmc", 1},
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{"ti,omap4-hsmmc", 1},
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{"ti,mmchs", 1},
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{NULL, 0},
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};
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/*
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* The MMCHS hardware has a few control and status registers at the beginning of
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* the device's memory map, followed by the standard sdhci register block.
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* Different SoCs have the register blocks at different offsets from the
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* beginning of the device. Define some constants to map out the registers we
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* access, and the various per-SoC offsets. The SDHCI_REG_OFFSET is how far
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* beyond the MMCHS block the SDHCI block is found; it's the same on all SoCs.
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*/
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#define OMAP3_MMCHS_REG_OFFSET 0x000
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#define OMAP4_MMCHS_REG_OFFSET 0x100
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#define AM335X_MMCHS_REG_OFFSET 0x100
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#define SDHCI_REG_OFFSET 0x100
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#define MMCHS_SYSCONFIG 0x010
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#define MMCHS_SYSCONFIG_RESET (1 << 1)
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#define MMCHS_SYSSTATUS 0x014
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#define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
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#define MMCHS_CON 0x02C
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#define MMCHS_CON_DW8 (1 << 5)
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#define MMCHS_CON_DVAL_8_4MS (3 << 9)
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#define MMCHS_CON_OD (1 << 0)
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#define MMCHS_SYSCTL 0x12C
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#define MMCHS_SYSCTL_CLKD_MASK 0x3FF
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#define MMCHS_SYSCTL_CLKD_SHIFT 6
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#define MMCHS_SD_CAPA 0x140
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#define MMCHS_SD_CAPA_VS18 (1 << 26)
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#define MMCHS_SD_CAPA_VS30 (1 << 25)
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#define MMCHS_SD_CAPA_VS33 (1 << 24)
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/* Forward declarations, CAM-relataed */
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// static void ti_sdhci_cam_poll(struct cam_sim *);
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// static void ti_sdhci_cam_action(struct cam_sim *, union ccb *);
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// static int ti_sdhci_cam_settran_settings(struct ti_sdhci_softc *sc, union ccb *);
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static inline uint32_t
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ti_mmchs_read_4(struct ti_sdhci_softc *sc, bus_size_t off)
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{
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return (bus_read_4(sc->mem_res, off + sc->mmchs_reg_off));
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}
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static inline void
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ti_mmchs_write_4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val)
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{
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bus_write_4(sc->mem_res, off + sc->mmchs_reg_off, val);
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}
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static inline uint32_t
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RD4(struct ti_sdhci_softc *sc, bus_size_t off)
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{
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return (bus_read_4(sc->mem_res, off + sc->sdhci_reg_off));
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}
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static inline void
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WR4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val)
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{
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bus_write_4(sc->mem_res, off + sc->sdhci_reg_off, val);
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}
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static uint8_t
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ti_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
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{
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struct ti_sdhci_softc *sc = device_get_softc(dev);
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return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff);
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}
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static uint16_t
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ti_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
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{
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struct ti_sdhci_softc *sc = device_get_softc(dev);
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uint32_t clkdiv, val32;
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/*
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* The MMCHS hardware has a non-standard interpretation of the sdclock
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* divisor bits. It uses the same bit positions as SDHCI 3.0 (15..6)
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* but doesn't split them into low:high fields. Instead they're a
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* single number in the range 0..1023 and the number is exactly the
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* clock divisor (with 0 and 1 both meaning divide by 1). The SDHCI
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* driver code expects a v2.0 or v3.0 divisor. The shifting and masking
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* here extracts the MMCHS representation from the hardware word, cleans
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* those bits out, applies the 2N adjustment, and plugs the result into
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* the bit positions for the 2.0 or 3.0 divisor in the returned register
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* value. The ti_sdhci_write_2() routine performs the opposite
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* transformation when the SDHCI driver writes to the register.
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*/
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if (off == SDHCI_CLOCK_CONTROL) {
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val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
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clkdiv = ((val32 >> MMCHS_SYSCTL_CLKD_SHIFT) &
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MMCHS_SYSCTL_CLKD_MASK) / 2;
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val32 &= ~(MMCHS_SYSCTL_CLKD_MASK << MMCHS_SYSCTL_CLKD_SHIFT);
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val32 |= (clkdiv & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
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if (slot->version >= SDHCI_SPEC_300)
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val32 |= ((clkdiv >> SDHCI_DIVIDER_MASK_LEN) &
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SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_HI_SHIFT;
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return (val32 & 0xffff);
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}
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/*
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* Standard 32-bit handling of command and transfer mode.
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*/
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if (off == SDHCI_TRANSFER_MODE) {
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return (sc->cmd_and_mode >> 16);
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} else if (off == SDHCI_COMMAND_FLAGS) {
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return (sc->cmd_and_mode & 0x0000ffff);
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}
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return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff);
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}
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static uint32_t
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ti_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
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{
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struct ti_sdhci_softc *sc = device_get_softc(dev);
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uint32_t val32;
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val32 = RD4(sc, off);
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/*
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* If we need to disallow highspeed mode due to the OMAP4 erratum, strip
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* that flag from the returned capabilities.
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*/
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if (off == SDHCI_CAPABILITIES && sc->disable_highspeed)
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val32 &= ~SDHCI_CAN_DO_HISPD;
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/*
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* Force the card-present state if necessary.
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*/
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if (off == SDHCI_PRESENT_STATE && sc->force_card_present)
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val32 |= SDHCI_CARD_PRESENT;
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return (val32);
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}
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static void
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ti_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
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uint32_t *data, bus_size_t count)
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{
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struct ti_sdhci_softc *sc = device_get_softc(dev);
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bus_read_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count);
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}
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static void
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ti_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off,
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uint8_t val)
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{
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struct ti_sdhci_softc *sc = device_get_softc(dev);
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uint32_t val32;
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#ifdef MMCCAM
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uint32_t newval32;
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if (off == SDHCI_HOST_CONTROL) {
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val32 = ti_mmchs_read_4(sc, MMCHS_CON);
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newval32 = val32;
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if (val & SDHCI_CTRL_8BITBUS) {
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device_printf(dev, "Custom-enabling 8-bit bus\n");
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newval32 |= MMCHS_CON_DW8;
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} else {
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device_printf(dev, "Custom-disabling 8-bit bus\n");
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newval32 &= ~MMCHS_CON_DW8;
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}
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if (newval32 != val32)
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ti_mmchs_write_4(sc, MMCHS_CON, newval32);
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}
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#endif
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val32 = RD4(sc, off & ~3);
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val32 &= ~(0xff << (off & 3) * 8);
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val32 |= (val << (off & 3) * 8);
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WR4(sc, off & ~3, val32);
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}
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static void
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ti_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
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uint16_t val)
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{
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struct ti_sdhci_softc *sc = device_get_softc(dev);
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uint32_t clkdiv, val32;
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/*
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* Translate between the hardware and SDHCI 2.0 or 3.0 representations
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* of the clock divisor. See the comments in ti_sdhci_read_2() for
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* details.
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*/
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if (off == SDHCI_CLOCK_CONTROL) {
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clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK;
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if (slot->version >= SDHCI_SPEC_300)
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clkdiv |= ((val >> SDHCI_DIVIDER_HI_SHIFT) &
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SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN;
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clkdiv *= 2;
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if (clkdiv > MMCHS_SYSCTL_CLKD_MASK)
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clkdiv = MMCHS_SYSCTL_CLKD_MASK;
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val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
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val32 &= 0xffff0000;
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val32 |= val & ~(MMCHS_SYSCTL_CLKD_MASK <<
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MMCHS_SYSCTL_CLKD_SHIFT);
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val32 |= clkdiv << MMCHS_SYSCTL_CLKD_SHIFT;
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WR4(sc, SDHCI_CLOCK_CONTROL, val32);
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return;
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}
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/*
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* Standard 32-bit handling of command and transfer mode.
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*/
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if (off == SDHCI_TRANSFER_MODE) {
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sc->cmd_and_mode = (sc->cmd_and_mode & 0xffff0000) |
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((uint32_t)val & 0x0000ffff);
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return;
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} else if (off == SDHCI_COMMAND_FLAGS) {
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sc->cmd_and_mode = (sc->cmd_and_mode & 0x0000ffff) |
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((uint32_t)val << 16);
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WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode);
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return;
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}
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val32 = RD4(sc, off & ~3);
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val32 &= ~(0xffff << (off & 3) * 8);
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val32 |= ((val & 0xffff) << (off & 3) * 8);
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WR4(sc, off & ~3, val32);
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}
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static void
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ti_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
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uint32_t val)
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{
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struct ti_sdhci_softc *sc = device_get_softc(dev);
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WR4(sc, off, val);
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}
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static void
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ti_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
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uint32_t *data, bus_size_t count)
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{
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struct ti_sdhci_softc *sc = device_get_softc(dev);
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bus_write_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count);
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}
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static void
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ti_sdhci_intr(void *arg)
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{
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struct ti_sdhci_softc *sc = arg;
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sdhci_generic_intr(&sc->slot);
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}
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static int
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ti_sdhci_update_ios(device_t brdev, device_t reqdev)
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{
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struct ti_sdhci_softc *sc = device_get_softc(brdev);
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struct sdhci_slot *slot;
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struct mmc_ios *ios;
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uint32_t val32, newval32;
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slot = device_get_ivars(reqdev);
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ios = &slot->host.ios;
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/*
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* There is an 8-bit-bus bit in the MMCHS control register which, when
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* set, overrides the 1 vs 4 bit setting in the standard SDHCI
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* registers. Set that bit first according to whether an 8-bit bus is
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* requested, then let the standard driver handle everything else.
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*/
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val32 = ti_mmchs_read_4(sc, MMCHS_CON);
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newval32 = val32;
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if (ios->bus_width == bus_width_8)
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newval32 |= MMCHS_CON_DW8;
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else
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newval32 &= ~MMCHS_CON_DW8;
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if (ios->bus_mode == opendrain)
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newval32 |= MMCHS_CON_OD;
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else /* if (ios->bus_mode == pushpull) */
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newval32 &= ~MMCHS_CON_OD;
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if (newval32 != val32)
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ti_mmchs_write_4(sc, MMCHS_CON, newval32);
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return (sdhci_generic_update_ios(brdev, reqdev));
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}
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static int
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ti_sdhci_get_ro(device_t brdev, device_t reqdev)
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{
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struct ti_sdhci_softc *sc = device_get_softc(brdev);
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if (sc->disable_readonly)
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return (0);
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return (sdhci_fdt_gpio_get_readonly(sc->gpio));
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}
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static bool
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ti_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot)
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{
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struct ti_sdhci_softc *sc = device_get_softc(dev);
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return (sdhci_fdt_gpio_get_present(sc->gpio));
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}
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static int
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ti_sdhci_detach(device_t dev)
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{
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/* sdhci_fdt_gpio_teardown(sc->gpio); */
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return (EBUSY);
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}
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static void
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ti_sdhci_hw_init(device_t dev)
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{
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struct ti_sdhci_softc *sc = device_get_softc(dev);
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uint32_t regval;
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unsigned long timeout;
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/* Enable the controller and interface/functional clocks */
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if (ti_prcm_clk_enable(sc->mmchs_clk_id) != 0) {
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device_printf(dev, "Error: failed to enable MMC clock\n");
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return;
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}
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/* Get the frequency of the source clock */
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if (ti_prcm_clk_get_source_freq(sc->mmchs_clk_id,
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&sc->baseclk_hz) != 0) {
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device_printf(dev, "Error: failed to get source clock freq\n");
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return;
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}
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/* Issue a softreset to the controller */
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ti_mmchs_write_4(sc, MMCHS_SYSCONFIG, MMCHS_SYSCONFIG_RESET);
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timeout = 1000;
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while (!(ti_mmchs_read_4(sc, MMCHS_SYSSTATUS) &
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MMCHS_SYSSTATUS_RESETDONE)) {
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if (--timeout == 0) {
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device_printf(dev,
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"Error: Controller reset operation timed out\n");
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break;
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}
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DELAY(100);
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}
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/*
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* Reset the command and data state machines and also other aspects of
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* the controller such as bus clock and power.
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*
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* If we read the software reset register too fast after writing it we
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* can get back a zero that means the reset hasn't started yet rather
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* than that the reset is complete. Per TI recommendations, work around
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* it by reading until we see the reset bit asserted, then read until
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* it's clear. We also set the SDHCI_QUIRK_WAITFOR_RESET_ASSERTED quirk
|
|
* so that the main sdhci driver uses this same logic in its resets.
|
|
*/
|
|
ti_sdhci_write_1(dev, NULL, SDHCI_SOFTWARE_RESET, SDHCI_RESET_ALL);
|
|
timeout = 10000;
|
|
while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) &
|
|
SDHCI_RESET_ALL) != SDHCI_RESET_ALL) {
|
|
if (--timeout == 0) {
|
|
break;
|
|
}
|
|
DELAY(1);
|
|
}
|
|
timeout = 10000;
|
|
while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) &
|
|
SDHCI_RESET_ALL)) {
|
|
if (--timeout == 0) {
|
|
device_printf(dev,
|
|
"Error: Software reset operation timed out\n");
|
|
break;
|
|
}
|
|
DELAY(100);
|
|
}
|
|
|
|
/*
|
|
* The attach() routine has examined fdt data and set flags in
|
|
* slot.host.caps to reflect what voltages we can handle. Set those
|
|
* values in the CAPA register. The manual says that these values can
|
|
* only be set once, "before initialization" whatever that means, and
|
|
* that they survive a reset. So maybe doing this will be a no-op if
|
|
* u-boot has already initialized the hardware.
|
|
*/
|
|
regval = ti_mmchs_read_4(sc, MMCHS_SD_CAPA);
|
|
if (sc->slot.host.caps & MMC_OCR_LOW_VOLTAGE)
|
|
regval |= MMCHS_SD_CAPA_VS18;
|
|
if (sc->slot.host.caps & (MMC_OCR_290_300 | MMC_OCR_300_310))
|
|
regval |= MMCHS_SD_CAPA_VS30;
|
|
ti_mmchs_write_4(sc, MMCHS_SD_CAPA, regval);
|
|
|
|
/* Set initial host configuration (1-bit, std speed, pwr off). */
|
|
ti_sdhci_write_1(dev, NULL, SDHCI_HOST_CONTROL, 0);
|
|
ti_sdhci_write_1(dev, NULL, SDHCI_POWER_CONTROL, 0);
|
|
|
|
/* Set the initial controller configuration. */
|
|
ti_mmchs_write_4(sc, MMCHS_CON, MMCHS_CON_DVAL_8_4MS);
|
|
}
|
|
|
|
static int
|
|
ti_sdhci_attach(device_t dev)
|
|
{
|
|
struct ti_sdhci_softc *sc = device_get_softc(dev);
|
|
int rid, err;
|
|
pcell_t prop;
|
|
phandle_t node;
|
|
|
|
sc->dev = dev;
|
|
|
|
/*
|
|
* Get the MMCHS device id from FDT. If it's not there use the newbus
|
|
* unit number (which will work as long as the devices are in order and
|
|
* none are skipped in the fdt). Note that this is a property we made
|
|
* up and added in freebsd, it doesn't exist in the published bindings.
|
|
*/
|
|
node = ofw_bus_get_node(dev);
|
|
sc->mmchs_clk_id = ti_hwmods_get_clock(dev);
|
|
if (sc->mmchs_clk_id == INVALID_CLK_IDENT) {
|
|
device_printf(dev, "failed to get clock based on hwmods property\n");
|
|
}
|
|
|
|
/*
|
|
* The hardware can inherently do dual-voltage (1p8v, 3p0v) on the first
|
|
* device, and only 1p8v on other devices unless an external transceiver
|
|
* is used. The only way we could know about a transceiver is fdt data.
|
|
* Note that we have to do this before calling ti_sdhci_hw_init() so
|
|
* that it can set the right values in the CAPA register, which can only
|
|
* be done once and never reset.
|
|
*/
|
|
sc->slot.host.caps |= MMC_OCR_LOW_VOLTAGE;
|
|
if (sc->mmchs_clk_id == MMC1_CLK || OF_hasprop(node, "ti,dual-volt")) {
|
|
sc->slot.host.caps |= MMC_OCR_290_300 | MMC_OCR_300_310;
|
|
}
|
|
|
|
/*
|
|
* Set the offset from the device's memory start to the MMCHS registers.
|
|
* Also for OMAP4 disable high speed mode due to erratum ID i626.
|
|
*/
|
|
switch (ti_chip()) {
|
|
#ifdef SOC_OMAP4
|
|
case CHIP_OMAP_4:
|
|
sc->mmchs_reg_off = OMAP4_MMCHS_REG_OFFSET;
|
|
sc->disable_highspeed = true;
|
|
break;
|
|
#endif
|
|
#ifdef SOC_TI_AM335X
|
|
case CHIP_AM335X:
|
|
sc->mmchs_reg_off = AM335X_MMCHS_REG_OFFSET;
|
|
break;
|
|
#endif
|
|
default:
|
|
panic("Unknown OMAP device\n");
|
|
}
|
|
|
|
/*
|
|
* The standard SDHCI registers are at a fixed offset (the same on all
|
|
* SoCs) beyond the MMCHS registers.
|
|
*/
|
|
sc->sdhci_reg_off = sc->mmchs_reg_off + SDHCI_REG_OFFSET;
|
|
|
|
/* Resource setup. */
|
|
rid = 0;
|
|
sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
|
|
RF_ACTIVE);
|
|
if (!sc->mem_res) {
|
|
device_printf(dev, "cannot allocate memory window\n");
|
|
err = ENXIO;
|
|
goto fail;
|
|
}
|
|
|
|
rid = 0;
|
|
sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
|
|
RF_ACTIVE);
|
|
if (!sc->irq_res) {
|
|
device_printf(dev, "cannot allocate interrupt\n");
|
|
err = ENXIO;
|
|
goto fail;
|
|
}
|
|
|
|
if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
|
|
NULL, ti_sdhci_intr, sc, &sc->intr_cookie)) {
|
|
device_printf(dev, "cannot setup interrupt handler\n");
|
|
err = ENXIO;
|
|
goto fail;
|
|
}
|
|
|
|
/*
|
|
* Set up handling of card-detect and write-protect gpio lines.
|
|
*
|
|
* If there is no write protect info in the fdt data, fall back to the
|
|
* historical practice of assuming that the card is writable. This
|
|
* works around bad fdt data from the upstream source. The alternative
|
|
* would be to trust the sdhci controller's PRESENT_STATE register WP
|
|
* bit, but it may say write protect is in effect when it's not if the
|
|
* pinmux setup doesn't route the WP signal into the sdchi block.
|
|
*/
|
|
sc->gpio = sdhci_fdt_gpio_setup(sc->dev, &sc->slot);
|
|
|
|
if (!OF_hasprop(node, "wp-gpios") && !OF_hasprop(node, "wp-disable"))
|
|
sc->disable_readonly = true;
|
|
|
|
/* Initialise the MMCHS hardware. */
|
|
ti_sdhci_hw_init(dev);
|
|
|
|
/*
|
|
* The capabilities register can only express base clock frequencies in
|
|
* the range of 0-63MHz for a v2.0 controller. Since our clock runs
|
|
* faster than that, the hardware sets the frequency to zero in the
|
|
* register. When the register contains zero, the sdhci driver expects
|
|
* slot.max_clk to already have the right value in it.
|
|
*/
|
|
sc->slot.max_clk = sc->baseclk_hz;
|
|
|
|
/*
|
|
* The MMCHS timeout counter is based on the output sdclock. Tell the
|
|
* sdhci driver to recalculate the timeout clock whenever the output
|
|
* sdclock frequency changes.
|
|
*/
|
|
sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
|
|
|
|
/*
|
|
* The MMCHS hardware shifts the 136-bit response data (in violation of
|
|
* the spec), so tell the sdhci driver not to do the same in software.
|
|
*/
|
|
sc->slot.quirks |= SDHCI_QUIRK_DONT_SHIFT_RESPONSE;
|
|
|
|
/*
|
|
* Reset bits are broken, have to wait to see the bits asserted
|
|
* before waiting to see them de-asserted.
|
|
*/
|
|
sc->slot.quirks |= SDHCI_QUIRK_WAITFOR_RESET_ASSERTED;
|
|
|
|
/*
|
|
* The controller waits for busy responses.
|
|
*/
|
|
sc->slot.quirks |= SDHCI_QUIRK_WAIT_WHILE_BUSY;
|
|
|
|
/*
|
|
* DMA is not really broken, I just haven't implemented it yet.
|
|
*/
|
|
sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA;
|
|
|
|
/*
|
|
* Set up the hardware and go. Note that this sets many of the
|
|
* slot.host.* fields, so we have to do this before overriding any of
|
|
* those values based on fdt data, below.
|
|
*/
|
|
sdhci_init_slot(dev, &sc->slot, 0);
|
|
|
|
/*
|
|
* The SDHCI controller doesn't realize it, but we can support 8-bit
|
|
* even though we're not a v3.0 controller. If there's an fdt bus-width
|
|
* property, honor it.
|
|
*/
|
|
if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) {
|
|
sc->slot.host.caps &= ~(MMC_CAP_4_BIT_DATA |
|
|
MMC_CAP_8_BIT_DATA);
|
|
switch (prop) {
|
|
case 8:
|
|
sc->slot.host.caps |= MMC_CAP_8_BIT_DATA;
|
|
/* FALLTHROUGH */
|
|
case 4:
|
|
sc->slot.host.caps |= MMC_CAP_4_BIT_DATA;
|
|
break;
|
|
case 1:
|
|
break;
|
|
default:
|
|
device_printf(dev, "Bad bus-width value %u\n", prop);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* If the slot is flagged with the non-removable property, set our flag
|
|
* to always force the SDHCI_CARD_PRESENT bit on.
|
|
*/
|
|
node = ofw_bus_get_node(dev);
|
|
if (OF_hasprop(node, "non-removable"))
|
|
sc->force_card_present = true;
|
|
|
|
bus_generic_probe(dev);
|
|
bus_generic_attach(dev);
|
|
|
|
sdhci_start_slot(&sc->slot);
|
|
return (0);
|
|
|
|
fail:
|
|
if (sc->intr_cookie)
|
|
bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
|
|
if (sc->irq_res)
|
|
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
|
|
if (sc->mem_res)
|
|
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
|
|
|
|
return (err);
|
|
}
|
|
|
|
static int
|
|
ti_sdhci_probe(device_t dev)
|
|
{
|
|
|
|
if (!ofw_bus_status_okay(dev))
|
|
return (ENXIO);
|
|
|
|
if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
|
|
device_set_desc(dev, "TI MMCHS (SDHCI 2.0)");
|
|
return (BUS_PROBE_DEFAULT);
|
|
}
|
|
|
|
return (ENXIO);
|
|
}
|
|
|
|
static device_method_t ti_sdhci_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, ti_sdhci_probe),
|
|
DEVMETHOD(device_attach, ti_sdhci_attach),
|
|
DEVMETHOD(device_detach, ti_sdhci_detach),
|
|
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
|
|
DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
|
|
|
|
/* MMC bridge interface */
|
|
DEVMETHOD(mmcbr_update_ios, ti_sdhci_update_ios),
|
|
DEVMETHOD(mmcbr_request, sdhci_generic_request),
|
|
DEVMETHOD(mmcbr_get_ro, ti_sdhci_get_ro),
|
|
DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
|
|
DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
|
|
|
|
/* SDHCI registers accessors */
|
|
DEVMETHOD(sdhci_read_1, ti_sdhci_read_1),
|
|
DEVMETHOD(sdhci_read_2, ti_sdhci_read_2),
|
|
DEVMETHOD(sdhci_read_4, ti_sdhci_read_4),
|
|
DEVMETHOD(sdhci_read_multi_4, ti_sdhci_read_multi_4),
|
|
DEVMETHOD(sdhci_write_1, ti_sdhci_write_1),
|
|
DEVMETHOD(sdhci_write_2, ti_sdhci_write_2),
|
|
DEVMETHOD(sdhci_write_4, ti_sdhci_write_4),
|
|
DEVMETHOD(sdhci_write_multi_4, ti_sdhci_write_multi_4),
|
|
DEVMETHOD(sdhci_get_card_present, ti_sdhci_get_card_present),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static devclass_t ti_sdhci_devclass;
|
|
|
|
static driver_t ti_sdhci_driver = {
|
|
"sdhci_ti",
|
|
ti_sdhci_methods,
|
|
sizeof(struct ti_sdhci_softc),
|
|
};
|
|
|
|
DRIVER_MODULE(sdhci_ti, simplebus, ti_sdhci_driver, ti_sdhci_devclass, NULL,
|
|
NULL);
|
|
MODULE_DEPEND(sdhci_ti, sdhci, 1, 1, 1);
|
|
|
|
#ifndef MMCCAM
|
|
MMC_DECLARE_BRIDGE(sdhci_ti);
|
|
#endif
|