9e0c3bdf64
value was only enough for 8GB of RAM, the new value can do 16GB. This still isn't optimal since it doesn't scale. Fixing this for amd64 looks to be fairly easy, but for i386 will be quite difficult. Reviewed by: peter
362 lines
9.8 KiB
C
362 lines
9.8 KiB
C
/*
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* Copyright (c) 1991 Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department and William Jolitz of UUNET Technologies Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Derived from hp300 version by Mike Hibler, this version by William
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* Jolitz uses a recursive map [a pde points to the page directory] to
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* map the page tables using the pagetables themselves. This is done to
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* reduce the impact on kernel virtual memory for lots of sparse address
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* space, and to reduce the cost of memory to each process.
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*
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* from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90
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* from: @(#)pmap.h 7.4 (Berkeley) 5/12/91
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PMAP_H_
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#define _MACHINE_PMAP_H_
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/*
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* Page-directory and page-table entires follow this format, with a few
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* of the fields not present here and there, depending on a lot of things.
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*/
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/* ---- Intel Nomenclature ---- */
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#define PG_V 0x001 /* P Valid */
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#define PG_RW 0x002 /* R/W Read/Write */
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#define PG_U 0x004 /* U/S User/Supervisor */
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#define PG_NC_PWT 0x008 /* PWT Write through */
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#define PG_NC_PCD 0x010 /* PCD Cache disable */
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#define PG_A 0x020 /* A Accessed */
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#define PG_M 0x040 /* D Dirty */
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#define PG_PS 0x080 /* PS Page size (0=4k,1=4M) */
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#define PG_G 0x100 /* G Global */
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#define PG_AVAIL1 0x200 /* / Available for system */
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#define PG_AVAIL2 0x400 /* < programmers use */
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#define PG_AVAIL3 0x800 /* \ */
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/* Our various interpretations of the above */
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#define PG_W PG_AVAIL1 /* "Wired" pseudoflag */
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#define PG_MANAGED PG_AVAIL2
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#define PG_FRAME (~((vm_paddr_t)PAGE_MASK))
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#define PG_PROT (PG_RW|PG_U) /* all protection bits . */
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#define PG_N (PG_NC_PWT|PG_NC_PCD) /* Non-cacheable */
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/*
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* Page Protection Exception bits
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*/
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#define PGEX_P 0x01 /* Protection violation vs. not present */
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#define PGEX_W 0x02 /* during a Write cycle */
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#define PGEX_U 0x04 /* access from User mode (UPL) */
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/*
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* Size of Kernel address space. This is the number of page table pages
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* (4MB each) to use for the kernel. 256 pages == 1 Gigabyte.
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* This **MUST** be a multiple of 4 (eg: 252, 256, 260, etc).
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*/
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#ifndef KVA_PAGES
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#ifdef PAE
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#define KVA_PAGES 512
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#else
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#define KVA_PAGES 256
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#endif
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#endif
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/*
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* Pte related macros
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*/
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#define VADDR(pdi, pti) ((vm_offset_t)(((pdi)<<PDRSHIFT)|((pti)<<PAGE_SHIFT)))
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/* Actual number of kernel page tables */
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#ifndef NKPT
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#ifdef PAE
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#define NKPT 240 /* Enough for 16GB (2MB page tables) */
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#else
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#define NKPT 30 /* Enough for 4GB (4MB page tables) */
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#endif
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#endif
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#ifndef NKPDE
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#ifdef SMP
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#define NKPDE (KVA_PAGES - 1) /* number of page tables/pde's */
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#else
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#define NKPDE (KVA_PAGES) /* number of page tables/pde's */
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#endif
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#endif
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/*
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* The *PTDI values control the layout of virtual memory
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*
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* XXX This works for now, but I am not real happy with it, I'll fix it
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* right after I fix locore.s and the magic 28K hole
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*
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* SMP_PRIVPAGES: The per-cpu address space is 0xff80000 -> 0xffbfffff
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*/
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#ifdef SMP
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#define MPPTDI (NPDEPTD-1) /* per cpu ptd entry */
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#define KPTDI (MPPTDI-NKPDE) /* start of kernel virtual pde's */
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#else
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#define KPTDI (NPDEPTD-NKPDE)/* start of kernel virtual pde's */
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#endif /* SMP */
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#define PTDPTDI (KPTDI-NPGPTD) /* ptd entry that points to ptd! */
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/*
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* XXX doesn't really belong here I guess...
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*/
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#define ISA_HOLE_START 0xa0000
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#define ISA_HOLE_LENGTH (0x100000-ISA_HOLE_START)
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#ifndef LOCORE
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#include <sys/queue.h>
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#include <sys/_lock.h>
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#include <sys/_mutex.h>
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#ifdef PAE
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typedef uint64_t pdpt_entry_t;
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typedef uint64_t pd_entry_t;
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typedef uint64_t pt_entry_t;
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#define PTESHIFT (3)
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#define PDESHIFT (3)
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#else
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typedef uint32_t pd_entry_t;
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typedef uint32_t pt_entry_t;
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#define PTESHIFT (2)
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#define PDESHIFT (2)
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#endif
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/*
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* Address of current and alternate address space page table maps
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* and directories.
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*/
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#ifdef _KERNEL
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extern pt_entry_t PTmap[];
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extern pd_entry_t PTD[];
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extern pd_entry_t PTDpde[];
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#ifdef PAE
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extern pdpt_entry_t *IdlePDPT;
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#endif
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extern pd_entry_t *IdlePTD; /* physical address of "Idle" state directory */
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#endif
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#ifdef _KERNEL
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/*
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* virtual address to page table entry and
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* to physical address. Likewise for alternate address space.
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* Note: these work recursively, thus vtopte of a pte will give
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* the corresponding pde that in turn maps it.
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*/
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#define vtopte(va) (PTmap + i386_btop(va))
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/*
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* Routine: pmap_kextract
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* Function:
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* Extract the physical page address associated
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* kernel virtual address.
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*/
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static __inline vm_paddr_t
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pmap_kextract(vm_offset_t va)
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{
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vm_paddr_t pa;
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if ((pa = PTD[va >> PDRSHIFT]) & PG_PS) {
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pa = (pa & ~(NBPDR - 1)) | (va & (NBPDR - 1));
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} else {
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pa = *vtopte(va);
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pa = (pa & PG_FRAME) | (va & PAGE_MASK);
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}
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return pa;
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}
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#define vtophys(va) pmap_kextract(((vm_offset_t) (va)))
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#ifdef PAE
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static __inline pt_entry_t
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pte_load(pt_entry_t *ptep)
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{
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pt_entry_t r;
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__asm __volatile(
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"lock; cmpxchg8b %1"
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: "=A" (r)
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: "m" (*ptep), "a" (0), "d" (0), "b" (0), "c" (0));
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return (r);
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}
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static __inline pt_entry_t
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pte_load_store(pt_entry_t *ptep, pt_entry_t v)
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{
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pt_entry_t r;
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r = *ptep;
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__asm __volatile(
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"1:\n"
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"\tlock; cmpxchg8b %1\n"
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"\tjnz 1b"
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: "+A" (r)
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: "m" (*ptep), "b" ((uint32_t)v), "c" ((uint32_t)(v >> 32)));
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return (r);
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}
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#define pte_load_clear(ptep) pte_load_store((ptep), (pt_entry_t)0ULL)
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#else /* PAE */
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static __inline pt_entry_t
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pte_load(pt_entry_t *ptep)
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{
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pt_entry_t r;
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r = *ptep;
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return (r);
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}
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static __inline pt_entry_t
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pte_load_store(pt_entry_t *ptep, pt_entry_t pte)
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{
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pt_entry_t r;
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r = *ptep;
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*ptep = pte;
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return (r);
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}
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#define pte_load_clear(pte) atomic_readandclear_int(pte)
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#endif /* PAE */
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#define pte_clear(ptep) pte_load_store((ptep), (pt_entry_t)0ULL)
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#define pte_store(ptep, pte) pte_load_store((ptep), (pt_entry_t)pte)
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#define pde_store(pdep, pde) pte_store((pdep), (pde))
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#endif /* _KERNEL */
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/*
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* Pmap stuff
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*/
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struct pv_entry;
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struct md_page {
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int pv_list_count;
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TAILQ_HEAD(,pv_entry) pv_list;
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};
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struct pmap {
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struct mtx pm_mtx;
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pd_entry_t *pm_pdir; /* KVA of page directory */
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TAILQ_HEAD(,pv_entry) pm_pvlist; /* list of mappings in pmap */
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u_int pm_active; /* active on cpus */
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struct pmap_statistics pm_stats; /* pmap statistics */
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LIST_ENTRY(pmap) pm_list; /* List of all pmaps */
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#ifdef PAE
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pdpt_entry_t *pm_pdpt; /* KVA of page director pointer
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table */
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#endif
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};
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typedef struct pmap *pmap_t;
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#ifdef _KERNEL
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extern struct pmap kernel_pmap_store;
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#define kernel_pmap (&kernel_pmap_store)
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#define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx)
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#define PMAP_LOCK_ASSERT(pmap, type) \
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mtx_assert(&(pmap)->pm_mtx, (type))
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#define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx)
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#define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \
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NULL, MTX_DEF)
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#define PMAP_LOCKED(pmap) mtx_owned(&(pmap)->pm_mtx)
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#define PMAP_MTX(pmap) (&(pmap)->pm_mtx)
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#define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx)
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#define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx)
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#endif
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/*
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* For each vm_page_t, there is a list of all currently valid virtual
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* mappings of that page. An entry is a pv_entry_t, the list is pv_table.
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*/
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typedef struct pv_entry {
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pmap_t pv_pmap; /* pmap where mapping lies */
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vm_offset_t pv_va; /* virtual address for mapping */
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TAILQ_ENTRY(pv_entry) pv_list;
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TAILQ_ENTRY(pv_entry) pv_plist;
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} *pv_entry_t;
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#ifdef _KERNEL
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#define NPPROVMTRR 8
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#define PPRO_VMTRRphysBase0 0x200
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#define PPRO_VMTRRphysMask0 0x201
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struct ppro_vmtrr {
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u_int64_t base, mask;
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};
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extern struct ppro_vmtrr PPro_vmtrr[NPPROVMTRR];
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extern caddr_t CADDR1;
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extern pt_entry_t *CMAP1;
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extern vm_paddr_t avail_end;
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extern vm_paddr_t phys_avail[];
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extern int pseflag;
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extern int pgeflag;
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extern char *ptvmmap; /* poor name! */
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extern vm_offset_t virtual_avail;
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extern vm_offset_t virtual_end;
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#define pmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list))
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void pmap_bootstrap(vm_paddr_t, vm_paddr_t);
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void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
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void *pmap_kenter_temporary(vm_paddr_t pa, int i);
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void pmap_kremove(vm_offset_t);
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void *pmap_mapdev(vm_paddr_t, vm_size_t);
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void pmap_unmapdev(vm_offset_t, vm_size_t);
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pt_entry_t *pmap_pte(pmap_t, vm_offset_t) __pure2;
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void pmap_set_pg(void);
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void pmap_invalidate_page(pmap_t, vm_offset_t);
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void pmap_invalidate_range(pmap_t, vm_offset_t, vm_offset_t);
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void pmap_invalidate_all(pmap_t);
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#endif /* _KERNEL */
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#endif /* !LOCORE */
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#endif /* !_MACHINE_PMAP_H_ */
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