f60708c9f7
Summary: PowerPC Book-E SMP is currently broken for unknown reasons. Pull in Semihalf changes made c2012 for e500mc/e5500, which enables booting SMP. This eliminates the shared software TLB1 table, replacing it with tlb1_read_entry() function. This does not yet support ePAPR SMP booting, and doesn't handle resetting CPUs already released (ePAPR boot releases APs to a spin loop waiting on a specific address). This will be addressed in the near future by using the MPIC to reset the AP into our own alternate boot address. This does include a change to the dpaa/dtsec(4) driver, to mark the portals as CPU-private. Test Plan: Tested on Amiga X5000/20 (P5020). Boots, prints the following messages: Adding CPU 0, pir=0, awake=1 Waking up CPU 1 (dev=1) Adding CPU 1, pir=20, awake=1 SMP: AP CPU #1 launched top(1) shows CPU1 active. Obtained from: Semihalf Relnotes: Yes Differential Revision: https://reviews.freebsd.org/D5945
228 lines
6.6 KiB
C
228 lines
6.6 KiB
C
/*-
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* Copyright (C) 2006-2012 Semihalf.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_TLB_H_
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#define _MACHINE_TLB_H_
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#if defined(BOOKE_E500)
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/* PowerPC E500 MAS registers */
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#define MAS0_TLBSEL(x) ((x << 28) & 0x10000000)
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#define MAS0_ESEL(x) ((x << 16) & 0x003F0000)
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#define MAS0_TLBSEL1 0x10000000
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#define MAS0_TLBSEL0 0x00000000
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#define MAS0_ESEL_TLB1MASK 0x000F0000
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#define MAS0_ESEL_TLB0MASK 0x00030000
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#define MAS0_ESEL_SHIFT 16
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#define MAS0_NV_MASK 0x00000003
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#define MAS0_NV_SHIFT 0
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#define MAS1_VALID 0x80000000
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#define MAS1_IPROT 0x40000000
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#define MAS1_TID_MASK 0x00FF0000
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#define MAS1_TID_SHIFT 16
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#define MAS1_TS_MASK 0x00001000
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#define MAS1_TS_SHIFT 12
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#define MAS1_TSIZE_MASK 0x00000F00
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#define MAS1_TSIZE_SHIFT 8
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#define TLB_SIZE_4K 1
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#define TLB_SIZE_16K 2
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#define TLB_SIZE_64K 3
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#define TLB_SIZE_256K 4
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#define TLB_SIZE_1M 5
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#define TLB_SIZE_4M 6
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#define TLB_SIZE_16M 7
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#define TLB_SIZE_64M 8
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#define TLB_SIZE_256M 9
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#define TLB_SIZE_1G 10
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#define TLB_SIZE_4G 11
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#define MAS2_EPN_MASK 0xFFFFF000
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#define MAS2_EPN_SHIFT 12
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#define MAS2_X0 0x00000040
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#define MAS2_X1 0x00000020
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#define MAS2_W 0x00000010
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#define MAS2_I 0x00000008
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#define MAS2_M 0x00000004
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#define MAS2_G 0x00000002
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#define MAS2_E 0x00000001
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#define MAS2_WIMGE_MASK 0x0000007F
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#define MAS3_RPN 0xFFFFF000
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#define MAS3_RPN_SHIFT 12
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#define MAS3_U0 0x00000200
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#define MAS3_U1 0x00000100
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#define MAS3_U2 0x00000080
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#define MAS3_U3 0x00000040
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#define MAS3_UX 0x00000020
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#define MAS3_SX 0x00000010
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#define MAS3_UW 0x00000008
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#define MAS3_SW 0x00000004
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#define MAS3_UR 0x00000002
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#define MAS3_SR 0x00000001
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#define MAS4_TLBSELD1 0x10000000
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#define MAS4_TLBSELD0 0x00000000
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#define MAS4_TIDSELD_MASK 0x00030000
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#define MAS4_TIDSELD_SHIFT 16
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#define MAS4_TSIZED_MASK 0x00000F00
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#define MAS4_TSIZED_SHIFT 8
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#define MAS4_X0D 0x00000040
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#define MAS4_X1D 0x00000020
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#define MAS4_WD 0x00000010
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#define MAS4_ID 0x00000008
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#define MAS4_MD 0x00000004
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#define MAS4_GD 0x00000002
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#define MAS4_ED 0x00000001
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#define MAS6_SPID0_MASK 0x00FF0000
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#define MAS6_SPID0_SHIFT 16
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#define MAS6_SAS 0x00000001
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#define MAS7_RPN 0x0000000F
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#define MAS1_GETTID(mas1) (((mas1) & MAS1_TID_MASK) >> MAS1_TID_SHIFT)
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#define MAS2_TLB0_ENTRY_IDX_MASK 0x0007f000
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#define MAS2_TLB0_ENTRY_IDX_SHIFT 12
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/*
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* Maximum number of TLB1 entries used for a permanent mapping of kernel
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* region (kernel image plus statically allocated data).
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*/
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#define KERNEL_REGION_MAX_TLB_ENTRIES 4
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/*
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* Use MAS2_X0 to mark entries which will be copied
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* to AP CPUs during SMP bootstrap. As result entries
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* marked with _TLB_ENTRY_SHARED will be shared by all CPUs.
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*/
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#define _TLB_ENTRY_SHARED (MAS2_X0) /* XXX under SMP? */
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#define _TLB_ENTRY_IO (MAS2_I | MAS2_G)
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#define _TLB_ENTRY_MEM (MAS2_M)
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#define TLB1_MAX_ENTRIES 64
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#if !defined(LOCORE)
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typedef struct tlb_entry {
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vm_paddr_t phys;
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vm_offset_t virt;
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vm_size_t size;
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uint32_t mas1;
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uint32_t mas2;
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uint32_t mas3;
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uint32_t mas7;
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} tlb_entry_t;
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void tlb0_print_tlbentries(void);
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void tlb1_inval_entry(unsigned int);
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void tlb1_init(void);
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void tlb1_print_entries(void);
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void tlb1_print_tlbentries(void);
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#endif /* !LOCORE */
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#elif defined(BOOKE_PPC4XX)
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/* TLB Words */
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#define TLB_PAGEID 0
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#define TLB_XLAT 1
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#define TLB_ATTRIB 2
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/* Page identification fields */
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#define TLB_EPN_MASK (0xFFFFFC00 >> 0)
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#define TLB_VALID (0x80000000 >> 22)
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#define TLB_TS (0x80000000 >> 23)
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#define TLB_SIZE_1K (0x00000000 >> 24)
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#define TLB_SIZE_MASK (0xF0000000 >> 24)
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/* Translation fields */
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#define TLB_RPN_MASK (0xFFFFFC00 >> 0)
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#define TLB_ERPN_MASK (0xF0000000 >> 28)
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/* Storage attribute and access control fields */
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#define TLB_WL1 (0x80000000 >> 11)
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#define TLB_IL1I (0x80000000 >> 12)
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#define TLB_IL1D (0x80000000 >> 13)
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#define TLB_IL2I (0x80000000 >> 14)
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#define TLB_IL2D (0x80000000 >> 15)
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#define TLB_U0 (0x80000000 >> 16)
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#define TLB_U1 (0x80000000 >> 17)
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#define TLB_U2 (0x80000000 >> 18)
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#define TLB_U3 (0x80000000 >> 19)
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#define TLB_W (0x80000000 >> 20)
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#define TLB_I (0x80000000 >> 21)
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#define TLB_M (0x80000000 >> 22)
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#define TLB_G (0x80000000 >> 23)
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#define TLB_E (0x80000000 >> 24)
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#define TLB_UX (0x80000000 >> 26)
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#define TLB_UW (0x80000000 >> 27)
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#define TLB_UR (0x80000000 >> 28)
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#define TLB_SX (0x80000000 >> 29)
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#define TLB_SW (0x80000000 >> 30)
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#define TLB_SR (0x80000000 >> 31)
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#define TLB_SIZE 64
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#define TLB_SIZE_4K (0x10000000 >> 24)
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#define TLB_SIZE_16K (0x20000000 >> 24)
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#define TLB_SIZE_64K (0x30000000 >> 24)
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#define TLB_SIZE_256K (0x40000000 >> 24)
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#define TLB_SIZE_1M (0x50000000 >> 24)
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#define TLB_SIZE_16M (0x70000000 >> 24)
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#define TLB_SIZE_256M (0x90000000 >> 24)
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#define TLB_SIZE_1G (0xA0000000 >> 24)
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#endif /* BOOKE_E500 */
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#define TID_KERNEL 0 /* TLB TID to use for kernel (shared) translations */
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#define TID_KRESERVED 1 /* Number of TIDs reserved for kernel */
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#define TID_URESERVED 0 /* Number of TIDs reserved for user */
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#define TID_MIN (TID_KRESERVED + TID_URESERVED)
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#define TID_MAX 255
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#define TID_NONE -1
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#define TLB_UNLOCKED 0
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#if !defined(LOCORE)
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typedef int tlbtid_t;
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struct pmap;
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void tlb_lock(uint32_t *);
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void tlb_unlock(uint32_t *);
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void tlb1_ap_prep(void);
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int tlb1_set_entry(vm_offset_t, vm_paddr_t, vm_size_t, uint32_t);
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#endif /* !LOCORE */
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#endif /* _MACHINE_TLB_H_ */
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