a106c6930a
useful for accessing more than 1 page of contiguous physical memory, and to use 4mb tlb entries instead of 8k. This requires that the system only use the direct mapped addresses when they have the same virtual colour as all other mappings of the same page, instead of being able to choose the colour and cachability of the mapping. - Adapt the physical page copying and zeroing functions to account for not being able to choose the colour or cachability of the direct mapped address. This adds a lot more cases to handle. Basically when a page has a different colour than its direct mapped address we have a choice between bypassing the data cache and using physical addresses directly, which requires a cache flush, or mapping it at the right colour, which requires a tlb flush. For now we choose to map the page and do the tlb flush. This will allows the direct mapped addresses to be used for more things that don't require normal pmap handling, including mapping the vm_page structures, the message buffer, temporary mappings for crash dumps, and will provide greater benefit for implementing uma_small_alloc, due to the much greater tlb coverage.
110 lines
3.8 KiB
C
110 lines
3.8 KiB
C
/*-
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* Copyright (c) 2001 Jake Burkholder.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_TLB_H_
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#define _MACHINE_TLB_H_
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#define TLB_DIRECT_ADDRESS_BITS (43)
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#define TLB_DIRECT_PAGE_BITS (PAGE_SHIFT_4M)
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#define TLB_DIRECT_ADDRESS_MASK ((1UL << TLB_DIRECT_ADDRESS_BITS) - 1)
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#define TLB_DIRECT_PAGE_MASK ((1UL << TLB_DIRECT_PAGE_BITS) - 1)
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#define TLB_PHYS_TO_DIRECT(pa) \
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((pa) | VM_MIN_DIRECT_ADDRESS)
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#define TLB_DIRECT_TO_PHYS(va) \
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((va) & TLB_DIRECT_ADDRESS_MASK)
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#define TLB_DIRECT_TO_TTE_MASK \
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(TD_V | TD_4M | (TLB_DIRECT_ADDRESS_MASK - TLB_DIRECT_PAGE_MASK))
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#define TLB_DAR_SLOT_SHIFT (3)
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#define TLB_DAR_SLOT(slot) ((slot) << TLB_DAR_SLOT_SHIFT)
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#define TAR_VPN_SHIFT (13)
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#define TAR_CTX_MASK ((1 << TAR_VPN_SHIFT) - 1)
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#define TLB_TAR_VA(va) ((va) & ~TAR_CTX_MASK)
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#define TLB_TAR_CTX(ctx) ((ctx) & TAR_CTX_MASK)
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#define TLB_DEMAP_ID_SHIFT (4)
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#define TLB_DEMAP_ID_PRIMARY (0)
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#define TLB_DEMAP_ID_SECONDARY (1)
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#define TLB_DEMAP_ID_NUCLEUS (2)
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#define TLB_DEMAP_TYPE_SHIFT (6)
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#define TLB_DEMAP_TYPE_PAGE (0)
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#define TLB_DEMAP_TYPE_CONTEXT (1)
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#define TLB_DEMAP_VA(va) ((va) & ~PAGE_MASK)
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#define TLB_DEMAP_ID(id) ((id) << TLB_DEMAP_ID_SHIFT)
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#define TLB_DEMAP_TYPE(type) ((type) << TLB_DEMAP_TYPE_SHIFT)
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#define TLB_DEMAP_PAGE (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_PAGE))
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#define TLB_DEMAP_CONTEXT (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_CONTEXT))
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#define TLB_DEMAP_PRIMARY (TLB_DEMAP_ID(TLB_DEMAP_ID_PRIMARY))
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#define TLB_DEMAP_SECONDARY (TLB_DEMAP_ID(TLB_DEMAP_ID_SECONDARY))
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#define TLB_DEMAP_NUCLEUS (TLB_DEMAP_ID(TLB_DEMAP_ID_NUCLEUS))
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#define TLB_CTX_KERNEL (0)
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#define TLB_CTX_USER_MIN (1)
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#define TLB_CTX_USER_MAX (8192)
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#define MMU_SFSR_ASI_SHIFT (16)
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#define MMU_SFSR_FT_SHIFT (7)
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#define MMU_SFSR_E_SHIFT (6)
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#define MMU_SFSR_CT_SHIFT (4)
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#define MMU_SFSR_PR_SHIFT (3)
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#define MMU_SFSR_W_SHIFT (2)
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#define MMU_SFSR_OW_SHIFT (1)
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#define MMU_SFSR_FV_SHIFT (0)
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#define MMU_SFSR_ASI_SIZE (8)
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#define MMU_SFSR_FT_SIZE (6)
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#define MMU_SFSR_CT_SIZE (2)
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#define MMU_SFSR_GET_ASI(sfsr) \
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(((sfsr) >> MMU_SFSR_ASI_SHIFT) & ((1UL << MMU_SFSR_ASI_SIZE) - 1))
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#define MMU_SFSR_W (1UL << MMU_SFSR_W_SHIFT)
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#define MMU_SFSR_FV (1UL << MMU_SFSR_FV_SHIFT)
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struct tlb_entry;
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extern int kernel_tlb_slots;
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extern struct tlb_entry *kernel_tlbs;
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extern int tlb_dtlb_entries;
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extern int tlb_itlb_entries;
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void tlb_context_demap(struct pmap *pm);
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void tlb_page_demap(struct pmap *pm, vm_offset_t va);
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void tlb_range_demap(struct pmap *pm, vm_offset_t start, vm_offset_t end);
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void tlb_dump(void);
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#endif /* !_MACHINE_TLB_H_ */
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