170 lines
4.4 KiB
ArmAsm
170 lines
4.4 KiB
ArmAsm
/*-
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* Copyright (C) 2010 Nathan Whitehorn
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define LOCORE
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#include <machine/trap_aim.h>
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/*
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* KBoot and simulators will start this program from the _start symbol, with
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* r3 pointing to a flattened device tree (kexec), r4 the physical address
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* at which we were loaded, and r5 0 (kexec) or a pointer to Open Firmware
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* (simulator). If r4 is non-zero, the first order of business is relocating
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* ourselves to 0. In the kboot case, the PPE secondary thread will enter
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* at 0x60.
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*
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* If started directly by the LV1 hypervisor, we are loaded to address 0
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* and execution on both threads begins at 0x100 (EXC_RST).
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*/
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#define CACHELINE_SIZE 128
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#define SPR_CTRL 136
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/* KBoot thread 0 entry -- do relocation, then jump to main */
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.global _start
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_start:
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mfmsr %r31
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clrldi %r31,%r31,1
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mtmsrd %r31
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isync
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cmpwi %r4,0
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bne relocate_self
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relocated_start:
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lis %r1,0x100
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bl main
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. = 0x40
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.global secondary_spin_sem
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secondary_spin_sem:
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.long 0
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. = 0x60
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thread1_start_kboot:
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mfmsr %r31
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clrldi %r31,%r31,1
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mtmsrd %r31
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isync
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ba thread1_start /* kboot copies the first 256 bytes to
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* address 0, so we are safe to jump
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* (and stay) there */
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thread1_start:
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li %r3,secondary_spin_sem@l
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1: lwz %r1,0(%r3) /* Spin on SECONDARY_SPIN_SEM_ADDRESS */
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cmpwi %r1,0
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beq 1b /* If the semaphore is still zero, spin again */
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/* We have been woken up by thread 0 */
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li %r0,0x100 /* Invalidate reset vector cache line */
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icbi 0,%r0
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isync
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sync
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ba 0x100 /* Jump to the reset vector */
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. = EXC_RST
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exc_rst:
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mfmsr %r31
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clrldi %r31,%r31,1
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mtmsrd %r31
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isync
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mfspr %r3,SPR_CTRL
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/* The first two bits of r0 are 01 (thread 1) or 10 (thread 0) */
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cntlzw %r3,%r3 /* Now 0 for thread 0, 1 for thread 1 */
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cmpwi %r3,0
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bne thread1_start /* Send thread 1 to wait */
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b relocated_start /* Main entry point for thread 0 */
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#define EXCEPTION_HANDLER(exc) \
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. = exc; \
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li %r3, exc; \
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mfsrr0 %r4; \
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mfmsr %r5; \
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clrldi %r6,%r5,1; \
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mtmsrd %r6; \
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isync; \
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lis %r1,0x100; \
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bl ppc_exception
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EXCEPTION_HANDLER(EXC_MCHK)
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EXCEPTION_HANDLER(EXC_DSI)
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EXCEPTION_HANDLER(EXC_DSE)
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EXCEPTION_HANDLER(EXC_ISI)
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EXCEPTION_HANDLER(EXC_ISE)
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EXCEPTION_HANDLER(EXC_EXI)
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EXCEPTION_HANDLER(EXC_ALI)
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EXCEPTION_HANDLER(EXC_PGM)
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EXCEPTION_HANDLER(EXC_FPU)
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EXCEPTION_HANDLER(EXC_DECR)
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EXCEPTION_HANDLER(EXC_SC)
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relocate_self:
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/* We enter this with r4 the physical offset for our relocation */
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lis %r8,_end@ha /* r8: copy length */
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addi %r8,%r8,_end@l
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li %r5,0x100 /* r5: dest address */
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1: add %r6,%r4,%r5 /* r6: source address */
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ld %r7,0(%r6)
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std %r7,0(%r5)
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addi %r5,%r5,8
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cmpw %r5,%r8
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blt 1b
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/*
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* Now invalidate the cacheline with the second half of relocate_self,
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* and do an absolute branch there in case we overwrote part of
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* ourselves.
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*/
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lis %r9,relocate_self_cache@ha
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addi %r9,%r9,relocate_self_cache@l
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dcbst 0,%r9
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sync
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icbi 0,%r9
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sync
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isync
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ba relocate_self_cache
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relocate_self_cache:
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/* Now invalidate the icache */
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li %r5,0x100
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2: dcbst 0,%r5
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sync
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icbi 0,%r5
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sync
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isync
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cmpw %r5,%r8
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addi %r5,%r5,CACHELINE_SIZE
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blt 2b
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/* All done: absolute jump to relocated entry point */
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ba relocated_start
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