343044c43b
The A83T thermal sensor controller has three sensors. Sensor 0 corresponds to CPU cluster 0, sensor 1 to CPU cluster 1, and sensor 2 to the GPU. This driver exports the temperature sensor readings via sysctl. Calibration data is obtained from SRAM found in the Secure ID module. Reviewed by: manu Differential Revision: https://reviews.freebsd.org/D6378
244 lines
6.7 KiB
Plaintext
244 lines
6.7 KiB
Plaintext
/*-
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* Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/ {
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pmu {
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compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
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/* Cluster 0 only */
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interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
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};
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clocks {
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/* cpus_clk compatible in gnu dt is incorrect */
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cpus_clk: clk@01f01400 {
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compatible = "allwinner,sun8i-a83t-cpus-clk";
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};
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pll_hsic: clk@01c20044 {
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#clock-cells = <0>;
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compatible = "allwinner,sun9i-a80-pll4-clk";
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reg = <0x01c20044 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll_hsic";
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};
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usb_clk: clk@01c200cc {
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#clock-cells = <1>;
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#reset-cells = <1>;
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compatible = "allwinner,sun8i-a83t-usb-clk";
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reg = <0x01c200cc 0x4>;
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clocks = <&osc24M>, <&pll_hsic>;
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clock-indices = <8>, <9>,
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<10>, <11>,
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<16>;
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clock-output-names = "usb_phy0", "usb_phy1",
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"usb_hsic_pll", "usb_hsic_12m",
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"usb_ohci0";
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};
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mii_phy_tx_clk: clk@1 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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clock-output-names = "mii_phy_tx";
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};
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emac_int_tx_clk: clk@2 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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clock-output-names = "emac_int_tx";
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};
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emac_tx_clk: clk@01c00030 {
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#clock-cells = <0>;
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compatible = "allwinner,sun8i-a83t-emac-clk";
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reg = <0x01c00030 0x4>;
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clocks = <&mii_phy_tx_clk>, <&emac_int_tx_clk>;
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clock-output-names = "emac_tx";
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};
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};
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soc {
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nmi_intc: interrupt-controller@01f00c0c {
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compatible = "allwinner,sun6i-a31-sc-nmi";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x01f00c0c 0x38>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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};
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i2c0: i2c@01c2ac00 {
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compatible = "allwinner,sun8i-a83t-i2c";
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reg = <0x01c2ac00 0x400>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bus_gates 96>;
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resets = <&apb2_reset 0>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c1: i2c@01c2b000 {
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compatible = "allwinner,sun8i-a83t-i2c";
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reg = <0x01c2b000 0x400>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bus_gates 97>;
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resets = <&apb2_reset 1>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c2: i2c@01c2b400 {
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compatible = "allwinner,sun8i-a83t-i2c";
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reg = <0x01c2b400 0x400>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bus_gates 98>;
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resets = <&apb2_reset 2>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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usbphy: phy@01c19400 {
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compatible = "allwinner,sun8i-a83t-usb-phy";
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clocks = <&usb_clk 8>,
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<&usb_clk 9>,
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<&usb_clk 10>,
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<&usb_clk 11>;
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clock-names = "usb0_phy",
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"usb1_phy",
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"hsic_pll",
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"hsic_12m";
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resets = <&usb_clk 0>,
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<&usb_clk 1>,
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<&usb_clk 2>;
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reset-names = "usb0_reset",
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"usb1_reset",
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"usb2_reset";
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status = "disabled";
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#phy-cells = <1>;
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};
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ehci0: usb@01c1a000 {
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compatible = "allwinner,sun8i-a83t-ehci", "generic-ehci";
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reg = <0x01c1a000 0x100>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bus_gates 26>;
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resets = <&ahb_reset 26>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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ehci1: usb@01c1b000 {
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compatible = "allwinner,sun8i-a83t-ehci", "generic-ehci";
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reg = <0x01c1b000 0x100>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bus_gates 27>;
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resets = <&ahb_reset 27>;
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phys = <&usbphy 2>;
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phy-names = "usb";
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status = "disabled";
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};
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emac: ethernet@01c30000 {
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compatible = "allwinner,sun8i-a83t-emac";
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reg = <0x01c30000 0x100>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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clocks = <&bus_gates 17>, <&emac_tx_clk>;
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clock-names = "ahb", "tx";
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resets = <&ahb_reset 17>;
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reset-names = "ahb";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sid: eeprom@01c14000 {
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compatible = "allwinner,sun8i-a83t-sid";
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reg = <0x01c14000 0x400>;
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};
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rtp: rtp@01f04000 {
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compatible = "allwinner,sun8i-a83t-ts";
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reg = <0x01f04000 0x400>;
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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#thermal-sensor-cells = <0>;
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};
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};
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};
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&pio {
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mmc2_8bit_pins: mmc2_8bit {
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allwinner,pins = "PC5", "PC6", "PC8",
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"PC9", "PC10", "PC11",
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"PC12", "PC13", "PC14",
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"PC15", "PC16";
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allwinner,function = "mmc2";
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allwinner,drive = <SUN4I_PINCTRL_30_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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emac_pins_rgmii_a: emac_rgmii@0 {
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allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
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"PD11", "PD12", "PD13", "PD14",
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"PD18", "PD19", "PD20", "PD21", "PD22", "PD23";
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allwinner,function = "emac";
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allwinner,drive = <SUN4I_PINCTRL_40_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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i2c0_pins_a: i2c0@0 {
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allwinner,pins = "PH0", "PH1";
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allwinner,function = "i2c0";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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i2c1_pins_a: i2c1@0 {
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allwinner,pins = "PH2", "PH3";
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allwinner,function = "i2c1";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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i2c2_pins_a: i2c2@0 {
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allwinner,pins = "PH4", "PH5";
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allwinner,function = "i2c2";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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};
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