a1f8ad145e
applied to our copy of llvm/clang. These can be applied in alphabetical order to a pristine llvm/clang 3.4 release source tree, to result in the same version used in FreeBSD. This is intended to clearly document all the changes until now, which mostly consist of cherry pickings from the respective upstream trunks, plus a number of hand-written FreeBSD-specific ones. Hopefully those can eventually be cleaned up and sent upstream too. MFC after: 1 week X-MFC-With: r263313
148 lines
5.4 KiB
Diff
148 lines
5.4 KiB
Diff
Pull in r199028 from upstream llvm trunk (by Jakob Stoklund Olesen):
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The SPARCv9 ABI returns a float in %f0.
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This is different from the argument passing convention which puts the
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first float argument in %f1.
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With this patch, all returned floats are treated as if the 'inreg' flag
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were set. This means multiple float return values get packed in %f0,
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%f1, %f2, ...
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Note that when returning a struct in registers, clang will set the
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'inreg' flag on the return value, so that behavior is unchanged. This
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also happens when returning a float _Complex.
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Introduced here: http://svn.freebsd.org/changeset/base/262261
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Index: test/CodeGen/SPARC/64abi.ll
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===================================================================
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--- test/CodeGen/SPARC/64abi.ll
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+++ test/CodeGen/SPARC/64abi.ll
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@@ -180,7 +180,7 @@ define void @call_inreg_fi(i32* %p, i32 %i1, float
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}
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; CHECK: inreg_ff
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-; CHECK: fsubs %f0, %f1, %f1
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+; CHECK: fsubs %f0, %f1, %f0
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define float @inreg_ff(float inreg %a0, ; %f0
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float inreg %a1) { ; %f1
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%rv = fsub float %a0, %a1
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@@ -262,10 +262,10 @@ define void @call_ret_i64_pair(i64* %i0) {
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ret void
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}
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-; This is not a C struct, each member uses 8 bytes.
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+; This is not a C struct, the i32 member uses 8 bytes, but the float only 4.
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; CHECK: ret_i32_float_pair
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; CHECK: ld [%i2], %i0
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-; CHECK: ld [%i3], %f3
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+; CHECK: ld [%i3], %f2
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define { i32, float } @ret_i32_float_pair(i32 %a0, i32 %a1,
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i32* %p, float* %q) {
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%r1 = load i32* %p
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@@ -279,7 +279,7 @@ define { i32, float } @ret_i32_float_pair(i32 %a0,
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; CHECK: call_ret_i32_float_pair
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; CHECK: call ret_i32_float_pair
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; CHECK: st %o0, [%i0]
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-; CHECK: st %f3, [%i1]
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+; CHECK: st %f2, [%i1]
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define void @call_ret_i32_float_pair(i32* %i0, float* %i1) {
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%rv = call { i32, float } @ret_i32_float_pair(i32 undef, i32 undef,
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i32* undef, float* undef)
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Index: test/CodeGen/SPARC/constpool.ll
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===================================================================
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--- test/CodeGen/SPARC/constpool.ll
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+++ test/CodeGen/SPARC/constpool.ll
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@@ -21,7 +21,7 @@ entry:
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; abs44: add %[[R1]], %m44(.LCPI0_0), %[[R2:[gilo][0-7]]]
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; abs44: sllx %[[R2]], 12, %[[R3:[gilo][0-7]]]
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; abs44: retl
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-; abs44: ld [%[[R3]]+%l44(.LCPI0_0)], %f1
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+; abs44: ld [%[[R3]]+%l44(.LCPI0_0)], %f0
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; abs64: floatCP
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@@ -31,7 +31,7 @@ entry:
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; abs64: add %[[R3]], %hm(.LCPI0_0), %[[R4:[gilo][0-7]]]
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; abs64: sllx %[[R4]], 32, %[[R5:[gilo][0-7]]]
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; abs64: retl
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-; abs64: ld [%[[R5]]+%[[R2]]], %f1
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+; abs64: ld [%[[R5]]+%[[R2]]], %f0
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; v8pic32: floatCP
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@@ -50,7 +50,7 @@ entry:
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; v9pic32: sethi %hi(.LCPI0_0), %[[R1:[gilo][0-7]]]
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; v9pic32: add %[[R1]], %lo(.LCPI0_0), %[[Goffs:[gilo][0-7]]]
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; v9pic32: ldx [%[[GOT:[gilo][0-7]]]+%[[Goffs]]], %[[Gaddr:[gilo][0-7]]]
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-; v9pic32: ld [%[[Gaddr]]], %f1
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+; v9pic32: ld [%[[Gaddr]]], %f0
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; v9pic32: ret
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; v9pic32: restore
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Index: test/CodeGen/SPARC/64cond.ll
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===================================================================
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--- test/CodeGen/SPARC/64cond.ll
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+++ test/CodeGen/SPARC/64cond.ll
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@@ -80,7 +80,7 @@ entry:
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; CHECK: selectf32_xcc
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; CHECK: cmp %i0, %i1
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; CHECK: fmovsg %xcc, %f5, %f7
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-; CHECK: fmovs %f7, %f1
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+; CHECK: fmovs %f7, %f0
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define float @selectf32_xcc(i64 %x, i64 %y, float %a, float %b) {
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entry:
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%tobool = icmp sgt i64 %x, %y
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Index: lib/Target/Sparc/SparcISelLowering.cpp
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===================================================================
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--- lib/Target/Sparc/SparcISelLowering.cpp
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+++ lib/Target/Sparc/SparcISelLowering.cpp
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@@ -254,7 +254,7 @@ SparcTargetLowering::LowerReturn_64(SDValue Chain,
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DAG.getTarget(), RVLocs, *DAG.getContext());
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// Analyze return values.
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- CCInfo.AnalyzeReturn(Outs, CC_Sparc64);
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+ CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64);
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SDValue Flag;
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SmallVector<SDValue, 4> RetOps(1, Chain);
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@@ -1258,7 +1258,7 @@ SparcTargetLowering::LowerCall_64(TargetLowering::
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if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && CLI.CS == 0)
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CLI.Ins[0].Flags.setInReg();
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- RVInfo.AnalyzeCallResult(CLI.Ins, CC_Sparc64);
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+ RVInfo.AnalyzeCallResult(CLI.Ins, RetCC_Sparc64);
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// Copy all of the result registers out of their specified physreg.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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Index: lib/Target/Sparc/SparcCallingConv.td
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===================================================================
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--- lib/Target/Sparc/SparcCallingConv.td
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+++ lib/Target/Sparc/SparcCallingConv.td
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@@ -103,7 +103,7 @@ def RetCC_Sparc32 : CallingConv<[
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// Function return values are passed exactly like function arguments, except a
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// struct up to 32 bytes in size can be returned in registers.
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-// Function arguments AND return values.
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+// Function arguments AND most return values.
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def CC_Sparc64 : CallingConv<[
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// The frontend uses the inreg flag to indicate i32 and float arguments from
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// structs. These arguments are not promoted to 64 bits, but they can still
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@@ -118,6 +118,15 @@ def CC_Sparc64 : CallingConv<[
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CCCustom<"CC_Sparc64_Full">
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]>;
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+def RetCC_Sparc64 : CallingConv<[
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+ // A single f32 return value always goes in %f0. The ABI doesn't specify what
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+ // happens to multiple f32 return values outside a struct.
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+ CCIfType<[f32], CCCustom<"CC_Sparc64_Half">>,
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+
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+ // Otherwise, return values are passed exactly like arguments.
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+ CCDelegateTo<CC_Sparc64>
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+]>;
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+
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// Callee-saved registers are handled by the register window mechanism.
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def CSR : CalleeSavedRegs<(add)> {
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let OtherPreserved = (add (sequence "I%u", 0, 7),
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