a1f8ad145e
applied to our copy of llvm/clang. These can be applied in alphabetical order to a pristine llvm/clang 3.4 release source tree, to result in the same version used in FreeBSD. This is intended to clearly document all the changes until now, which mostly consist of cherry pickings from the respective upstream trunks, plus a number of hand-written FreeBSD-specific ones. Hopefully those can eventually be cleaned up and sent upstream too. MFC after: 1 week X-MFC-With: r263313
143 lines
4.8 KiB
Diff
143 lines
4.8 KiB
Diff
Pull in r199781 from upstream llvm trunk (by Venkatraman Govindaraju):
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[Sparc] Add support for inline assembly constraint 'I'.
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Introduced here: http://svn.freebsd.org/changeset/base/262261
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Index: test/CodeGen/SPARC/inlineasm.ll
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===================================================================
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--- test/CodeGen/SPARC/inlineasm.ll
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+++ test/CodeGen/SPARC/inlineasm.ll
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@@ -0,0 +1,35 @@
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+; RUN: llc -march=sparc <%s | FileCheck %s
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+
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+; CHECK-LABEL: test_constraint_r
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+; CHECK: add %o1, %o0, %o0
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+define i32 @test_constraint_r(i32 %a, i32 %b) {
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+entry:
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+ %0 = tail call i32 asm sideeffect "add $2, $1, $0", "=r,r,r"(i32 %a, i32 %b)
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+ ret i32 %0
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+}
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+
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+; CHECK-LABEL: test_constraint_I
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+; CHECK: add %o0, 1023, %o0
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+define i32 @test_constraint_I(i32 %a) {
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+entry:
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+ %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 1023)
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+ ret i32 %0
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+}
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+
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+; CHECK-LABEL: test_constraint_I_neg
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+; CHECK: add %o0, -4096, %o0
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+define i32 @test_constraint_I_neg(i32 %a) {
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+entry:
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+ %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 -4096)
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+ ret i32 %0
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+}
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+
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+; CHECK-LABEL: test_constraint_I_largeimm
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+; CHECK: sethi 9, [[R0:%[gilo][0-7]]]
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+; CHECK: or [[R0]], 784, [[R1:%[gilo][0-7]]]
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+; CHECK: add %o0, [[R1]], %o0
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+define i32 @test_constraint_I_largeimm(i32 %a) {
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+entry:
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+ %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 10000)
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+ ret i32 %0
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+}
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Index: lib/Target/Sparc/SparcISelLowering.h
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===================================================================
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--- lib/Target/Sparc/SparcISelLowering.h
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+++ lib/Target/Sparc/SparcISelLowering.h
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@@ -73,6 +73,13 @@ namespace llvm {
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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ConstraintType getConstraintType(const std::string &Constraint) const;
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+ ConstraintWeight
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+ getSingleConstraintMatchWeight(AsmOperandInfo &info,
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+ const char *constraint) const;
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+ void LowerAsmOperandForConstraint(SDValue Op,
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+ std::string &Constraint,
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+ std::vector<SDValue> &Ops,
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+ SelectionDAG &DAG) const;
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
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Index: lib/Target/Sparc/SparcISelLowering.cpp
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===================================================================
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--- lib/Target/Sparc/SparcISelLowering.cpp
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+++ lib/Target/Sparc/SparcISelLowering.cpp
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@@ -2918,6 +2918,8 @@ SparcTargetLowering::getConstraintType(const std::
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switch (Constraint[0]) {
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default: break;
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case 'r': return C_RegisterClass;
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+ case 'I': // SIMM13
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+ return C_Other;
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}
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}
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@@ -2924,6 +2926,64 @@ SparcTargetLowering::getConstraintType(const std::
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return TargetLowering::getConstraintType(Constraint);
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}
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+TargetLowering::ConstraintWeight SparcTargetLowering::
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+getSingleConstraintMatchWeight(AsmOperandInfo &info,
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+ const char *constraint) const {
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+ ConstraintWeight weight = CW_Invalid;
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+ Value *CallOperandVal = info.CallOperandVal;
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+ // If we don't have a value, we can't do a match,
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+ // but allow it at the lowest weight.
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+ if (CallOperandVal == NULL)
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+ return CW_Default;
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+
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+ // Look at the constraint type.
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+ switch (*constraint) {
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+ default:
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+ weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
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+ break;
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+ case 'I': // SIMM13
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+ if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
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+ if (isInt<13>(C->getSExtValue()))
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+ weight = CW_Constant;
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+ }
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+ break;
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+ }
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+ return weight;
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+}
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+
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+/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
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+/// vector. If it is invalid, don't add anything to Ops.
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+void SparcTargetLowering::
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+LowerAsmOperandForConstraint(SDValue Op,
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+ std::string &Constraint,
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+ std::vector<SDValue> &Ops,
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+ SelectionDAG &DAG) const {
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+ SDValue Result(0, 0);
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+
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+ // Only support length 1 constraints for now.
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+ if (Constraint.length() > 1)
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+ return;
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+
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+ char ConstraintLetter = Constraint[0];
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+ switch (ConstraintLetter) {
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+ default: break;
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+ case 'I':
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+ if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
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+ if (isInt<13>(C->getSExtValue())) {
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+ Result = DAG.getTargetConstant(C->getSExtValue(), Op.getValueType());
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+ break;
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+ }
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+ return;
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+ }
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+ }
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+
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+ if (Result.getNode()) {
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+ Ops.push_back(Result);
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+ return;
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+ }
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+ TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
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+}
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+
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std::pair<unsigned, const TargetRegisterClass*>
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SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
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MVT VT) const {
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