13014ca04a
If you just config KERNEL as usual there should be no apparent changes, you'll get all chipset support code compiled in. However there is now a way to only compile in code for chipsets needed on a pr vendor basis. ATA now has the following "device" entries: atacore: ATA core functionality, always needed for any ATA setup atacard: CARDBUS support atacbus: PC98 cbus support ataisa: ISA bus support atapci: PCI bus support only generic chipset support. ataahci: AHCI support, also pulled in by some vendor modules. ataacard, ataacerlabs, ataadaptec, ataamd, ataati, atacenatek, atacypress, atacyrix, atahighpoint, ataintel, ataite, atajmicron, atamarvell, atamicron, atanational, atanetcell, atanvidia, atapromise, ataserverworks, atasiliconimage, atasis, atavia; Vendor support, ie atavia for VIA chipsets atadisk: ATA disk driver ataraid: ATA softraid driver atapicd: ATAPI cd/dvd driver atapifd: ATAPI floppy/flashdisk driver atapist: ATAPI tape driver atausb: ATA<>USB bridge atapicam: ATA<>CAM bridge This makes it possible to config a kernel with just VIA chipset support by having the following ATA lines in the kernel config file: device atacore device atapci device atavia And then you need the atadisk, atapicd etc lines in there just as usual. If you use ATA as modules loaded at boot there is few changes except the rename of the "ata" module to "atacore", things looks just as usual. However under atapci you now have a whole bunch of vendor specific drivers, that you can kldload individually depending on you needs. Drivers have the same names as used in the kernel config explained above.
265 lines
9.0 KiB
C
265 lines
9.0 KiB
C
/*-
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* Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ata.h"
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#include <sys/param.h>
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#include <sys/module.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/ata.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/malloc.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/sema.h>
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#include <sys/taskqueue.h>
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#include <vm/uma.h>
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#include <machine/stdarg.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/ata/ata-all.h>
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#include <dev/ata/ata-pci.h>
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#include <ata_if.h>
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/* local prototypes */
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static int ata_nvidia_chipinit(device_t dev);
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static int ata_nvidia_allocate(device_t dev);
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static int ata_nvidia_status(device_t dev);
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static void ata_nvidia_reset(device_t dev);
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static void ata_nvidia_setmode(device_t dev, int mode);
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/* misc defines */
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#define NV4 0x01
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#define NVQ 0x02
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/*
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* nVidia chipset support functions
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*/
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static int
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ata_nvidia_probe(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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static struct ata_chip_id ids[] =
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{{ ATA_NFORCE1, 0, 0, 0, ATA_UDMA5, "nForce" },
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{ ATA_NFORCE2, 0, 0, 0, ATA_UDMA6, "nForce2" },
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{ ATA_NFORCE2_PRO, 0, 0, 0, ATA_UDMA6, "nForce2 Pro" },
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{ ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" },
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{ ATA_NFORCE3, 0, 0, 0, ATA_UDMA6, "nForce3" },
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{ ATA_NFORCE3_PRO, 0, 0, 0, ATA_UDMA6, "nForce3 Pro" },
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{ ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
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{ ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
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{ ATA_NFORCE_MCP04, 0, 0, 0, ATA_UDMA6, "nForce MCP" },
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{ ATA_NFORCE_MCP04_S1, 0, NV4, 0, ATA_SA150, "nForce MCP" },
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{ ATA_NFORCE_MCP04_S2, 0, NV4, 0, ATA_SA150, "nForce MCP" },
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{ ATA_NFORCE_CK804, 0, 0, 0, ATA_UDMA6, "nForce CK804" },
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{ ATA_NFORCE_CK804_S1, 0, NV4, 0, ATA_SA300, "nForce CK804" },
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{ ATA_NFORCE_CK804_S2, 0, NV4, 0, ATA_SA300, "nForce CK804" },
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{ ATA_NFORCE_MCP51, 0, 0, 0, ATA_UDMA6, "nForce MCP51" },
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{ ATA_NFORCE_MCP51_S1, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP51" },
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{ ATA_NFORCE_MCP51_S2, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP51" },
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{ ATA_NFORCE_MCP55, 0, 0, 0, ATA_UDMA6, "nForce MCP55" },
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{ ATA_NFORCE_MCP55_S1, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP55" },
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{ ATA_NFORCE_MCP55_S2, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP55" },
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{ ATA_NFORCE_MCP61, 0, 0, 0, ATA_UDMA6, "nForce MCP61" },
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{ ATA_NFORCE_MCP61_S1, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP61" },
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{ ATA_NFORCE_MCP61_S2, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP61" },
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{ ATA_NFORCE_MCP61_S3, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP61" },
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{ ATA_NFORCE_MCP65, 0, 0, 0, ATA_UDMA6, "nForce MCP65" },
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{ ATA_NFORCE_MCP67, 0, 0, 0, ATA_UDMA6, "nForce MCP67" },
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{ ATA_NFORCE_MCP73, 0, 0, 0, ATA_UDMA6, "nForce MCP73" },
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{ ATA_NFORCE_MCP77, 0, 0, 0, ATA_UDMA6, "nForce MCP77" },
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{ 0, 0, 0, 0, 0, 0}} ;
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if (pci_get_vendor(dev) != ATA_NVIDIA_ID)
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return ENXIO;
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if (!(ctlr->chip = ata_match_chip(dev, ids)))
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return ENXIO;
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ata_set_desc(dev);
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ctlr->chipinit = ata_nvidia_chipinit;
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return 0;
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}
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static int
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ata_nvidia_chipinit(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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if (ata_setup_interrupt(dev, ata_generic_intr))
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return ENXIO;
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if (ctlr->chip->max_dma >= ATA_SA150) {
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if (pci_read_config(dev, PCIR_BAR(5), 1) & 1)
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ctlr->r_type2 = SYS_RES_IOPORT;
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else
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ctlr->r_type2 = SYS_RES_MEMORY;
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ctlr->r_rid2 = PCIR_BAR(5);
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if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
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&ctlr->r_rid2, RF_ACTIVE))) {
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int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010;
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ctlr->allocate = ata_nvidia_allocate;
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ctlr->reset = ata_nvidia_reset;
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/* enable control access */
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pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1);
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if (ctlr->chip->cfg1 & NVQ) {
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/* clear interrupt status */
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ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff);
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/* enable device and PHY state change interrupts */
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ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d);
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/* disable NCQ support */
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ATA_OUTL(ctlr->r_res2, 0x0400,
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ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9);
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}
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else {
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/* clear interrupt status */
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ATA_OUTB(ctlr->r_res2, offset, 0xff);
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/* enable device and PHY state change interrupts */
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ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd);
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}
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/* enable PCI interrupt */
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pci_write_config(dev, PCIR_COMMAND,
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pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
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}
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ctlr->setmode = ata_sata_setmode;
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}
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else {
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/* disable prefetch, postwrite */
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pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
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ctlr->setmode = ata_nvidia_setmode;
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}
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return 0;
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}
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static int
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ata_nvidia_allocate(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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/* setup the usual register normal pci style */
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if (ata_pci_allocate(dev))
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return ENXIO;
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ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
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ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6);
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ch->r_io[ATA_SERROR].res = ctlr->r_res2;
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ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6);
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ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
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ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6);
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ch->hw.status = ata_nvidia_status;
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ch->flags |= ATA_NO_SLAVE;
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return 0;
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}
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static int
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ata_nvidia_status(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010;
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int shift = ch->unit << (ctlr->chip->cfg1 & NVQ ? 4 : 2);
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u_int32_t istatus;
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/* get interrupt status */
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if (ctlr->chip->cfg1 & NVQ)
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istatus = ATA_INL(ctlr->r_res2, offset);
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else
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istatus = ATA_INB(ctlr->r_res2, offset);
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/* do we have any PHY events ? */
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if (istatus & (0x0c << shift))
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ata_sata_phy_check_events(dev);
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/* clear interrupt(s) */
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if (ctlr->chip->cfg1 & NVQ)
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ATA_OUTL(ctlr->r_res2, offset, (0x0f << shift) | 0x00f000f0);
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else
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ATA_OUTB(ctlr->r_res2, offset, (0x0f << shift));
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/* do we have any device action ? */
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return (istatus & (0x01 << shift));
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}
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static void
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ata_nvidia_reset(device_t dev)
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{
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if (ata_sata_phy_reset(dev))
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ata_generic_reset(dev);
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}
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static void
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ata_nvidia_setmode(device_t dev, int mode)
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{
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device_t gparent = GRANDPARENT(dev);
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struct ata_pci_controller *ctlr = device_get_softc(gparent);
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struct ata_channel *ch = device_get_softc(device_get_parent(dev));
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struct ata_device *atadev = device_get_softc(dev);
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u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
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0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
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int modes[7] = { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 };
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int devno = (ch->unit << 1) + atadev->unit;
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int reg = 0x63 - devno;
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int error;
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mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
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mode = ata_check_80pin(dev, mode);
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error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
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if (bootverbose)
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device_printf(dev, "%ssetting %s on %s chip\n",
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(error) ? "FAILURE " : "", ata_mode2str(mode),
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ctlr->chip->text);
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if (!error) {
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pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1);
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if (mode >= ATA_UDMA0)
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pci_write_config(gparent, reg, modes[mode & ATA_MODE_MASK], 1);
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else
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pci_write_config(gparent, reg, 0x8b, 1);
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atadev->mode = mode;
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}
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}
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ATA_DECLARE_DRIVER(ata_nvidia);
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