b812fe4d6b
This work, originally from Stacey Son, uses the MIPS UserReg for reading the TLS data, and will fall back to the normal syscall path when it isn't supported. This code dynamically patches cpu_switch() to bypass the UserReg instruction so to avoid generating a machine exception. Thanks to sson for the original work, and to Dan Nelson for bringing it to date and testing it on MIPS32 with me. Tested: * mips64 (sson) * mips74k (dnelson_1901@yahoo.com) - AR9344 SoC, UserReg support * mips24k (adrian) - AR9331 SoC, no UserReg support Obtained from: sson, dnelson_1901@yahoo.com
85 lines
2.8 KiB
C
85 lines
2.8 KiB
C
/* $NetBSD: cpu.h,v 1.70 2003/01/17 23:36:08 thorpej Exp $ */
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/*-
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell and Rick Macklem.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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* @(#)cpu.h 8.4 (Berkeley) 1/4/94
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*/
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#ifndef _CPUINFO_H_
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#define _CPUINFO_H_
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/*
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* Exported definitions unique to NetBSD/mips cpu support.
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*/
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#ifdef _KERNEL
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#ifndef LOCORE
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struct mips_cpuinfo {
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u_int8_t cpu_vendor;
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u_int8_t cpu_rev;
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u_int8_t cpu_impl;
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u_int8_t tlb_type;
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u_int32_t tlb_pgmask;
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u_int16_t tlb_nentries;
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u_int8_t icache_virtual;
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boolean_t cache_coherent_dma;
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boolean_t userlocal_reg;
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struct {
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u_int32_t ic_size;
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u_int8_t ic_linesize;
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u_int8_t ic_nways;
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u_int16_t ic_nsets;
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u_int32_t dc_size;
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u_int8_t dc_linesize;
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u_int8_t dc_nways;
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u_int16_t dc_nsets;
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} l1;
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struct {
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u_int32_t dc_size;
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u_int8_t dc_linesize;
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u_int8_t dc_nways;
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u_int16_t dc_nsets;
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} l2;
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};
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extern struct mips_cpuinfo cpuinfo;
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#endif /* !LOCORE */
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#endif /* _KERNEL */
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#endif /* _CPUINFO_H_ */
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