Tycho Nightingale 76b3c718be When ICW1 is issued the edge sense circuit is reset which means that ... following an initialization a low-to-high transistion is necesary to generate an interrupt. Reviewed by: neel		2015-03-06 02:05:45 +00:00
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amd	Fix warnings/errors when building vmm.ko with gcc:	2015-03-02 20:13:49 +00:00
intel	Always emulate MSR_PAT on Intel processors and don't rely on PAT save/restore	2015-02-24 05:35:15 +00:00
io	When ICW1 is issued the edge sense circuit is reset which means that	2015-03-06 02:05:45 +00:00
vmm_dev.c	Simplify instruction restart logic in bhyve.	2015-01-18 03:08:30 +00:00
vmm_host.c
vmm_host.h
vmm_instruction_emul.c	MOVS instruction emulation.	2015-01-19 06:53:31 +00:00
vmm_ioport.c	Fix typo (missing comma).	2015-01-14 07:18:51 +00:00
vmm_ioport.h	Change the type of the first argument to the I/O emulation handlers to	2014-10-26 19:03:06 +00:00
vmm_ipi.c
vmm_ipi.h
vmm_ktr.h
vmm_lapic.c
vmm_lapic.h
vmm_mem.c
vmm_mem.h
vmm_stat.c	Get rid of unused stat VMM_HLT_IGNORED.	2014-09-21 18:52:56 +00:00
vmm_stat.h	Get rid of unused stat VMM_HLT_IGNORED.	2014-09-21 18:52:56 +00:00
vmm_support.S	Add x2APIC support. Enable it by default if CPU is capable. The	2015-02-09 21:00:56 +00:00
vmm_util.c
vmm_util.h
vmm.c	Allow passthrough devices to be hinted.	2015-03-01 00:39:48 +00:00
x86.c	Don't advertise the "OS visible workarounds" feature in cpuid.80000001H:ECX.	2014-10-19 21:38:58 +00:00
x86.h