eba1cb6e3e
assign DMA address to the wrong address. It can cause system lockup or other mysterious errors. Since most sound cards requires low DMA address(BUS_SPACE_MAXADDR_24BIT) sndbuf_alloc() would fail when the audio driver is loaded after long running of operations. Approved by: jake (mentor) Reviewed by: truckman, matk
734 lines
19 KiB
C
734 lines
19 KiB
C
/*-
|
||
* Copyright (c) 2003 Dag-Erling Coïdan Smørgrav
|
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* All rights reserved.
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*
|
||
* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
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* are met:
|
||
* 1. Redistributions of source code must retain the above copyright
|
||
* notice, this list of conditions and the following disclaimer
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||
* in this position and unchanged.
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* 2. Redistributions in binary form must reproduce the above copyright
|
||
* notice, this list of conditions and the following disclaimer in the
|
||
* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <dev/sound/pcm/sound.h>
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#include <dev/sound/pcm/ac97.h>
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#include <dev/sound/pci/au88x0.h>
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#include <machine/bus.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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/***************************************************************************\
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* *
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* SUPPORTED CHIPSETS *
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* *
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\***************************************************************************/
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static struct au88x0_chipset au88x0_chipsets[] = {
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{
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.auc_name = "Aureal Vortex (8820)",
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.auc_pci_id = 0x000112eb,
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.auc_control = 0x1280c,
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.auc_irq_source = 0x12800,
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.auc_irq_mask = 0x12804,
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.auc_irq_control = 0x12808,
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.auc_irq_status = 0x1199c,
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.auc_dma_control = 0x1060c,
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.auc_fifo_size = 0x20,
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.auc_wt_fifos = 32,
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.auc_wt_fifo_base = 0x0e800,
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.auc_wt_fifo_ctl = 0x0f800,
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.auc_wt_dma_ctl = 0x10500,
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.auc_adb_fifos = 16,
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.auc_adb_fifo_base = 0x0e000,
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.auc_adb_fifo_ctl = 0x0f840,
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.auc_adb_dma_ctl = 0x10580,
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.auc_adb_route_base = 0x10800,
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.auc_adb_route_bits = 7,
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.auc_adb_codec_in = 0x48,
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.auc_adb_codec_out = 0x58,
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},
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{
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.auc_name = "Aureal Vortex 2 (8830)",
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.auc_pci_id = 0x000212eb,
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.auc_control = 0x2a00c,
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.auc_irq_source = 0x2a000,
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.auc_irq_mask = 0x2a004,
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.auc_irq_control = 0x2a008,
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.auc_irq_status = 0x2919c,
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.auc_dma_control = 0x27ae8,
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.auc_fifo_size = 0x40,
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.auc_wt_fifos = 64,
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.auc_wt_fifo_base = 0x10000,
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.auc_wt_fifo_ctl = 0x16000,
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.auc_wt_dma_ctl = 0x27900,
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.auc_adb_fifos = 32,
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.auc_adb_fifo_base = 0x14000,
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.auc_adb_fifo_ctl = 0x16100,
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.auc_adb_dma_ctl = 0x27a00,
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.auc_adb_route_base = 0x28000,
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.auc_adb_route_bits = 8,
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.auc_adb_codec_in = 0x70,
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.auc_adb_codec_out = 0x88,
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},
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{
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.auc_name = "Aureal Vortex Advantage (8810)",
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.auc_pci_id = 0x000312eb,
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.auc_control = 0x2a00c,
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.auc_irq_source = 0x2a000,
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.auc_irq_mask = 0x2a004,
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.auc_irq_control = 0x2a008,
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.auc_irq_status = 0x2919c,
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.auc_dma_control = 0x27ae8,
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.auc_fifo_size = 0x20,
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.auc_wt_fifos = 32,
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.auc_wt_fifo_base = 0x10000,
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.auc_wt_fifo_ctl = 0x16000,
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.auc_wt_dma_ctl = 0x27fd8,
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.auc_adb_fifos = 16,
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.auc_adb_fifo_base = 0x14000,
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.auc_adb_fifo_ctl = 0x16100,
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.auc_adb_dma_ctl = 0x27180,
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.auc_adb_route_base = 0x28000,
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.auc_adb_route_bits = 8,
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.auc_adb_codec_in = 0x70,
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.auc_adb_codec_out = 0x88,
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},
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{
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.auc_pci_id = 0,
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}
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};
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/***************************************************************************\
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* *
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* FORMATS AND CAPABILITIES *
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* *
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\***************************************************************************/
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static u_int32_t au88x0_formats[] = {
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AFMT_U8,
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AFMT_STEREO | AFMT_U8,
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AFMT_S16_LE,
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AFMT_STEREO | AFMT_S16_LE,
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0
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};
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static struct pcmchan_caps au88x0_capabilities = {
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4000, /* minimum sample rate */
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48000, /* maximum sample rate */
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au88x0_formats, /* supported formats */
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0 /* no particular capabilities */
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};
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/***************************************************************************\
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* *
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* CODEC INTERFACE *
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* *
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\***************************************************************************/
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/*
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* Read from the au88x0 register space
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*/
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#if 1
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/* all our writes are 32-bit */
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#define au88x0_read(aui, reg, n) \
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bus_space_read_4((aui)->aui_spct, (aui)->aui_spch, (reg))
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#define au88x0_write(aui, reg, data, n) \
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bus_space_write_4((aui)->aui_spct, (aui)->aui_spch, (reg), (data))
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#else
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static uint32_t
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au88x0_read(struct au88x0_info *aui, int reg, int size)
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{
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uint32_t data;
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switch (size) {
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case 1:
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data = bus_space_read_1(aui->aui_spct, aui->aui_spch, reg);
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break;
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case 2:
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data = bus_space_read_2(aui->aui_spct, aui->aui_spch, reg);
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break;
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case 4:
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data = bus_space_read_4(aui->aui_spct, aui->aui_spch, reg);
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break;
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default:
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panic("unsupported read size %d", size);
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}
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return (data);
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}
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/*
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* Write to the au88x0 register space
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*/
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static void
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au88x0_write(struct au88x0_info *aui, int reg, uint32_t data, int size)
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{
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switch (size) {
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case 1:
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bus_space_write_1(aui->aui_spct, aui->aui_spch, reg, data);
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break;
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case 2:
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bus_space_write_2(aui->aui_spct, aui->aui_spch, reg, data);
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break;
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case 4:
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bus_space_write_4(aui->aui_spct, aui->aui_spch, reg, data);
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break;
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default:
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panic("unsupported write size %d", size);
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}
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}
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#endif
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/*
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* Reset and initialize the codec
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*/
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static void
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au88x0_codec_init(struct au88x0_info *aui)
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{
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uint32_t data;
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int i;
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/* wave that chicken */
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au88x0_write(aui, AU88X0_CODEC_CONTROL, 0x8068, 4);
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DELAY(AU88X0_SETTLE_DELAY);
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au88x0_write(aui, AU88X0_CODEC_CONTROL, 0x00e8, 4);
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DELAY(1000);
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for (i = 0; i < 32; ++i) {
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au88x0_write(aui, AU88X0_CODEC_CHANNEL + i * 4, 0, 4);
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DELAY(AU88X0_SETTLE_DELAY);
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}
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au88x0_write(aui, AU88X0_CODEC_CONTROL, 0x00e8, 4);
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DELAY(AU88X0_SETTLE_DELAY);
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/* enable both codec channels */
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data = au88x0_read(aui, AU88X0_CODEC_ENABLE, 4);
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data |= (1 << (8 + 0)) | (1 << (8 + 1));
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au88x0_write(aui, AU88X0_CODEC_ENABLE, data, 4);
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DELAY(AU88X0_SETTLE_DELAY);
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}
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/*
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* Wait for the codec to get ready to accept a register write
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* Should be called at spltty
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*/
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static int
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au88x0_codec_wait(struct au88x0_info *aui)
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{
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uint32_t data;
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int i;
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for (i = 0; i < AU88X0_RETRY_COUNT; ++i) {
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data = au88x0_read(aui, AU88X0_CODEC_CONTROL, 4);
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if (data & AU88X0_CDCTL_WROK)
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return (0);
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DELAY(AU88X0_SETTLE_DELAY);
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}
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device_printf(aui->aui_dev, "timeout while waiting for codec\n");
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return (-1);
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}
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/*
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* Read from the ac97 codec
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*/
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static int
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au88x0_codec_read(kobj_t obj, void *arg, int reg)
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{
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struct au88x0_info *aui = arg;
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uint32_t data;
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int sl;
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sl = spltty();
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au88x0_codec_wait(aui);
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au88x0_write(aui, AU88X0_CODEC_IO, AU88X0_CDIO_READ(reg), 4);
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DELAY(1000);
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data = au88x0_read(aui, AU88X0_CODEC_IO, 4);
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splx(sl);
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data &= AU88X0_CDIO_DATA_MASK;
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data >>= AU88X0_CDIO_DATA_SHIFT;
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return (data);
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}
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/*
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* Write to the ac97 codec
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*/
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static int
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au88x0_codec_write(kobj_t obj, void *arg, int reg, uint32_t data)
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{
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struct au88x0_info *aui = arg;
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int sl;
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sl = spltty();
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au88x0_codec_wait(aui);
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au88x0_write(aui, AU88X0_CODEC_IO, AU88X0_CDIO_WRITE(reg, data), 4);
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splx(sl);
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return 0;
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}
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||
|
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/*
|
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* Codec interface glue
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*/
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static kobj_method_t au88x0_ac97_methods[] = {
|
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KOBJMETHOD(ac97_read, au88x0_codec_read),
|
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KOBJMETHOD(ac97_write, au88x0_codec_write),
|
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{ 0, 0 }
|
||
};
|
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AC97_DECLARE(au88x0_ac97);
|
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|
||
#define au88x0_channel(aui, dir) \
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&(aui)->aui_chan[((dir) == PCMDIR_PLAY) ? 0 : 1]
|
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|
||
|
||
/***************************************************************************\
|
||
* *
|
||
* CHANNEL INTERFACE *
|
||
* *
|
||
\***************************************************************************/
|
||
|
||
/*
|
||
* Initialize a PCM channel
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*/
|
||
static void *
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au88x0_chan_init(kobj_t obj, void *arg,
|
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struct snd_dbuf *buf, struct pcm_channel *chan, int dir)
|
||
{
|
||
struct au88x0_info *aui = arg;
|
||
struct au88x0_chan_info *auci = au88x0_channel(aui, dir);
|
||
|
||
if (sndbuf_alloc(buf, aui->aui_dmat, aui->aui_bufsize) != 0)
|
||
return (NULL);
|
||
auci->auci_aui = aui;
|
||
auci->auci_pcmchan = chan;
|
||
auci->auci_buf = buf;
|
||
auci->auci_dir = dir;
|
||
return (auci);
|
||
}
|
||
|
||
/*
|
||
* Set the data format for a PCM channel
|
||
*/
|
||
static int
|
||
au88x0_chan_setformat(kobj_t obj, void *arg, u_int32_t format)
|
||
{
|
||
|
||
/* XXX */
|
||
return (ENXIO);
|
||
}
|
||
|
||
/*
|
||
* Set the sample rate for a PCM channel
|
||
*/
|
||
static int
|
||
au88x0_chan_setspeed(kobj_t obj, void *arg, u_int32_t speed)
|
||
{
|
||
|
||
/* XXX */
|
||
return (speed);
|
||
}
|
||
|
||
/*
|
||
* Set the block size for a PCM channel
|
||
*/
|
||
static int
|
||
au88x0_chan_setblocksize(kobj_t obj, void *arg, u_int32_t blocksize)
|
||
{
|
||
|
||
/* XXX */
|
||
return (blocksize);
|
||
}
|
||
|
||
/*
|
||
* Initiate a data transfer
|
||
*/
|
||
static int
|
||
au88x0_chan_trigger(kobj_t obj, void *arg, int trigger)
|
||
{
|
||
struct au88x0_chan_info *auci = arg;
|
||
|
||
(void)auci;
|
||
switch (trigger) {
|
||
case PCMTRIG_START:
|
||
break;
|
||
case PCMTRIG_STOP:
|
||
case PCMTRIG_ABORT:
|
||
break;
|
||
}
|
||
return (0);
|
||
}
|
||
|
||
/*
|
||
*
|
||
*/
|
||
static int
|
||
au88x0_chan_getptr(kobj_t obj, void *arg)
|
||
{
|
||
|
||
/* XXX */
|
||
return (0);
|
||
}
|
||
|
||
/*
|
||
* Return the capabilities of a PCM channel
|
||
*/
|
||
static struct pcmchan_caps *
|
||
au88x0_chan_getcaps(kobj_t obj, void *arg)
|
||
{
|
||
|
||
return (&au88x0_capabilities);
|
||
}
|
||
|
||
/*
|
||
* Channel interface glue
|
||
*/
|
||
static kobj_method_t au88x0_chan_methods[] = {
|
||
KOBJMETHOD(channel_init, au88x0_chan_init),
|
||
KOBJMETHOD(channel_setformat, au88x0_chan_setformat),
|
||
KOBJMETHOD(channel_setspeed, au88x0_chan_setspeed),
|
||
KOBJMETHOD(channel_setblocksize, au88x0_chan_setblocksize),
|
||
KOBJMETHOD(channel_trigger, au88x0_chan_trigger),
|
||
KOBJMETHOD(channel_getptr, au88x0_chan_getptr),
|
||
KOBJMETHOD(channel_getcaps, au88x0_chan_getcaps),
|
||
{ 0, 0 }
|
||
};
|
||
CHANNEL_DECLARE(au88x0_chan);
|
||
|
||
|
||
/***************************************************************************\
|
||
* *
|
||
* INTERRUPT HANDLER *
|
||
* *
|
||
\***************************************************************************/
|
||
|
||
static void
|
||
au88x0_intr(void *arg)
|
||
{
|
||
struct au88x0_info *aui = arg;
|
||
struct au88x0_chipset *auc = aui->aui_chipset;
|
||
int pending, source;
|
||
|
||
pending = au88x0_read(aui, auc->auc_irq_control, 4);
|
||
if ((pending & AU88X0_IRQ_PENDING_BIT) == 0)
|
||
return;
|
||
source = au88x0_read(aui, auc->auc_irq_source, 4);
|
||
if (source & AU88X0_IRQ_FATAL_ERR)
|
||
device_printf(aui->aui_dev,
|
||
"fatal error interrupt received\n");
|
||
if (source & AU88X0_IRQ_PARITY_ERR)
|
||
device_printf(aui->aui_dev,
|
||
"parity error interrupt received\n");
|
||
/* XXX handle the others... */
|
||
|
||
/* acknowledge the interrupts we just handled */
|
||
au88x0_write(aui, auc->auc_irq_source, source, 4);
|
||
au88x0_read(aui, auc->auc_irq_source, 4);
|
||
}
|
||
|
||
|
||
/***************************************************************************\
|
||
* *
|
||
* INITIALIZATION *
|
||
* *
|
||
\***************************************************************************/
|
||
|
||
/*
|
||
* Reset and initialize the ADB and WT FIFOs
|
||
*
|
||
* - need to find out what the magic values 0x42000 and 0x2000 mean.
|
||
*/
|
||
static void
|
||
au88x0_fifo_init(struct au88x0_info *aui)
|
||
{
|
||
struct au88x0_chipset *auc = aui->aui_chipset;
|
||
int i;
|
||
|
||
/* reset, then clear the ADB FIFOs */
|
||
for (i = 0; i < auc->auc_adb_fifos; ++i)
|
||
au88x0_write(aui, auc->auc_adb_fifo_ctl + i * 4, 0x42000, 4);
|
||
for (i = 0; i < auc->auc_adb_fifos * auc->auc_fifo_size; ++i)
|
||
au88x0_write(aui, auc->auc_adb_fifo_base + i * 4, 0, 4);
|
||
|
||
/* reset, then clear the WT FIFOs */
|
||
for (i = 0; i < auc->auc_wt_fifos; ++i)
|
||
au88x0_write(aui, auc->auc_wt_fifo_ctl + i * 4, 0x42000, 4);
|
||
for (i = 0; i < auc->auc_wt_fifos * auc->auc_fifo_size; ++i)
|
||
au88x0_write(aui, auc->auc_wt_fifo_base + i * 4, 0, 4);
|
||
}
|
||
|
||
/*
|
||
* Hardware initialization
|
||
*/
|
||
static void
|
||
au88x0_init(struct au88x0_info *aui)
|
||
{
|
||
struct au88x0_chipset *auc = aui->aui_chipset;
|
||
|
||
/* reset the chip */
|
||
au88x0_write(aui, auc->auc_control, 0xffffffff, 4);
|
||
DELAY(10000);
|
||
|
||
/* clear all interrupts */
|
||
au88x0_write(aui, auc->auc_irq_source, 0xffffffff, 4);
|
||
au88x0_read(aui, auc->auc_irq_source, 4);
|
||
au88x0_read(aui, auc->auc_irq_status, 4);
|
||
|
||
/* initialize the codec */
|
||
au88x0_codec_init(aui);
|
||
|
||
/* initialize the fifos */
|
||
au88x0_fifo_init(aui);
|
||
|
||
/* initialize the DMA engine */
|
||
/* XXX chicken-waving! */
|
||
au88x0_write(aui, auc->auc_dma_control, 0x1380000, 4);
|
||
}
|
||
|
||
/*
|
||
* Construct and set status string
|
||
*/
|
||
static void
|
||
au88x0_set_status(device_t dev)
|
||
{
|
||
char status[SND_STATUSLEN];
|
||
struct au88x0_info *aui;
|
||
|
||
aui = pcm_getdevinfo(dev);
|
||
snprintf(status, sizeof status, "at %s 0x%lx irq %ld %s",
|
||
(aui->aui_regtype == SYS_RES_IOPORT)? "io" : "memory",
|
||
rman_get_start(aui->aui_reg), rman_get_start(aui->aui_irq),PCM_KLDSTRING(snd_au88x0));
|
||
pcm_setstatus(dev, status);
|
||
}
|
||
|
||
|
||
/***************************************************************************\
|
||
* *
|
||
* PCI INTERFACE *
|
||
* *
|
||
\***************************************************************************/
|
||
|
||
/*
|
||
* Probe
|
||
*/
|
||
static int
|
||
au88x0_pci_probe(device_t dev)
|
||
{
|
||
struct au88x0_chipset *auc;
|
||
uint32_t pci_id;
|
||
|
||
pci_id = pci_get_devid(dev);
|
||
for (auc = au88x0_chipsets; auc->auc_pci_id; ++auc) {
|
||
if (auc->auc_pci_id == pci_id) {
|
||
device_set_desc(dev, auc->auc_name);
|
||
return (0);
|
||
}
|
||
}
|
||
return (ENXIO);
|
||
}
|
||
|
||
/*
|
||
* Attach
|
||
*/
|
||
static int
|
||
au88x0_pci_attach(device_t dev)
|
||
{
|
||
struct au88x0_chipset *auc;
|
||
struct au88x0_info *aui = NULL;
|
||
uint32_t config;
|
||
int error;
|
||
|
||
if ((aui = malloc(sizeof *aui, M_DEVBUF, M_NOWAIT|M_ZERO)) == NULL) {
|
||
device_printf(dev, "failed to allocate softc\n");
|
||
return (ENXIO);
|
||
}
|
||
aui->aui_dev = dev;
|
||
|
||
/* Model-specific parameters */
|
||
aui->aui_model = pci_get_devid(dev);
|
||
for (auc = au88x0_chipsets; auc->auc_pci_id; ++auc)
|
||
if (auc->auc_pci_id == aui->aui_model)
|
||
aui->aui_chipset = auc;
|
||
if (aui->aui_chipset == NULL)
|
||
panic("%s() called for non-au88x0 device", __func__);
|
||
|
||
/* enable pio, mmio, bus-mastering dma */
|
||
config = pci_read_config(dev, PCIR_COMMAND, 2);
|
||
config |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
|
||
pci_write_config(dev, PCIR_COMMAND, config, 2);
|
||
|
||
/* register mapping */
|
||
config = pci_read_config(dev, PCIR_COMMAND, 2);
|
||
if (config & PCIM_CMD_MEMEN) {
|
||
/* try memory-mapped I/O */
|
||
aui->aui_regid = PCIR_BAR(0);
|
||
aui->aui_regtype = SYS_RES_MEMORY;
|
||
aui->aui_reg = bus_alloc_resource_any(dev, aui->aui_regtype,
|
||
&aui->aui_regid, RF_ACTIVE);
|
||
}
|
||
if (aui->aui_reg == NULL && (config & PCIM_CMD_PORTEN)) {
|
||
/* fall back on port I/O */
|
||
aui->aui_regid = PCIR_BAR(0);
|
||
aui->aui_regtype = SYS_RES_IOPORT;
|
||
aui->aui_reg = bus_alloc_resource_any(dev, aui->aui_regtype,
|
||
&aui->aui_regid, RF_ACTIVE);
|
||
}
|
||
if (aui->aui_reg == NULL) {
|
||
/* both mmio and pio failed... */
|
||
device_printf(dev, "failed to map registers\n");
|
||
goto failed;
|
||
}
|
||
aui->aui_spct = rman_get_bustag(aui->aui_reg);
|
||
aui->aui_spch = rman_get_bushandle(aui->aui_reg);
|
||
|
||
/* IRQ mapping */
|
||
aui->aui_irqid = 0;
|
||
aui->aui_irqtype = SYS_RES_IRQ;
|
||
aui->aui_irq = bus_alloc_resource_any(dev, aui->aui_irqtype,
|
||
&aui->aui_irqid, RF_ACTIVE | RF_SHAREABLE);
|
||
if (aui->aui_irq == 0) {
|
||
device_printf(dev, "failed to map IRQ\n");
|
||
goto failed;
|
||
}
|
||
|
||
/* install interrupt handler */
|
||
error = snd_setup_intr(dev, aui->aui_irq, 0, au88x0_intr,
|
||
aui, &aui->aui_irqh);
|
||
if (error != 0) {
|
||
device_printf(dev, "failed to install interrupt handler\n");
|
||
goto failed;
|
||
}
|
||
|
||
/* DMA mapping */
|
||
aui->aui_bufsize = pcm_getbuffersize(dev, AU88X0_BUFSIZE_MIN,
|
||
AU88X0_BUFSIZE_DFLT, AU88X0_BUFSIZE_MAX);
|
||
error = bus_dma_tag_create(NULL,
|
||
2, 0, /* 16-bit alignment, no boundary */
|
||
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, /* restrict to 4GB */
|
||
NULL, NULL, /* no filter */
|
||
aui->aui_bufsize, 1, aui->aui_bufsize,
|
||
0, busdma_lock_mutex, &Giant, &aui->aui_dmat);
|
||
if (error != 0) {
|
||
device_printf(dev, "failed to create DMA tag\n");
|
||
goto failed;
|
||
}
|
||
|
||
/* initialize the hardware */
|
||
au88x0_init(aui);
|
||
|
||
/* initialize the ac97 codec and mixer */
|
||
if ((aui->aui_ac97i = AC97_CREATE(dev, aui, au88x0_ac97)) == NULL) {
|
||
device_printf(dev, "failed to initialize ac97 codec\n");
|
||
goto failed;
|
||
}
|
||
if (mixer_init(dev, ac97_getmixerclass(), aui->aui_ac97i) != 0) {
|
||
device_printf(dev, "failed to initialize ac97 mixer\n");
|
||
goto failed;
|
||
}
|
||
|
||
/* register with the pcm driver */
|
||
if (pcm_register(dev, aui, 0, 0))
|
||
goto failed;
|
||
pcm_addchan(dev, PCMDIR_PLAY, &au88x0_chan_class, aui);
|
||
#if 0
|
||
pcm_addchan(dev, PCMDIR_REC, &au88x0_chan_class, aui);
|
||
#endif
|
||
au88x0_set_status(dev);
|
||
|
||
return (0);
|
||
failed:
|
||
if (aui->aui_ac97i != NULL)
|
||
ac97_destroy(aui->aui_ac97i);
|
||
if (aui->aui_dmat)
|
||
bus_dma_tag_destroy(aui->aui_dmat);
|
||
if (aui->aui_irqh != NULL)
|
||
bus_teardown_intr(dev, aui->aui_irq, aui->aui_irqh);
|
||
if (aui->aui_irq)
|
||
bus_release_resource(dev, aui->aui_irqtype,
|
||
aui->aui_irqid, aui->aui_irq);
|
||
if (aui->aui_reg)
|
||
bus_release_resource(dev, aui->aui_regtype,
|
||
aui->aui_regid, aui->aui_reg);
|
||
free(aui, M_DEVBUF);
|
||
return (ENXIO);
|
||
}
|
||
|
||
/*
|
||
* Detach
|
||
*/
|
||
static int
|
||
au88x0_pci_detach(device_t dev)
|
||
{
|
||
struct au88x0_info *aui;
|
||
int error;
|
||
|
||
aui = pcm_getdevinfo(dev);
|
||
if ((error = pcm_unregister(dev)) != 0)
|
||
return (error);
|
||
|
||
/* release resources in reverse order */
|
||
bus_dma_tag_destroy(aui->aui_dmat);
|
||
bus_teardown_intr(dev, aui->aui_irq, aui->aui_irqh);
|
||
bus_release_resource(dev, aui->aui_irqtype,
|
||
aui->aui_irqid, aui->aui_irq);
|
||
bus_release_resource(dev, aui->aui_regtype,
|
||
aui->aui_regid, aui->aui_reg);
|
||
free(aui, M_DEVBUF);
|
||
|
||
return (0);
|
||
}
|
||
|
||
/*
|
||
* Driver glue
|
||
*/
|
||
static device_method_t au88x0_methods[] = {
|
||
DEVMETHOD(device_probe, au88x0_pci_probe),
|
||
DEVMETHOD(device_attach, au88x0_pci_attach),
|
||
DEVMETHOD(device_detach, au88x0_pci_detach),
|
||
{ 0, 0 }
|
||
};
|
||
|
||
static driver_t au88x0_driver = {
|
||
"pcm",
|
||
au88x0_methods,
|
||
PCM_SOFTC_SIZE,
|
||
};
|
||
|
||
DRIVER_MODULE(snd_au88x0, pci, au88x0_driver, pcm_devclass, 0, 0);
|
||
MODULE_DEPEND(snd_au88x0, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
|
||
MODULE_VERSION(snd_au88x0, 1);
|