a2ffe82f1d
- Let creator_bitblt() return ENODEV as it's not implemented (missed in sys/dev/fb/creator.c rev. 1.6). - As a speed optimization inline the creator_ras_wait() etc. helper functions and also cache setting the font increment, font width and plane mask. [1] - I got the meaning of V_DISPLAY_BLANK wrong, it's blank like turn off and not blank like turn on and clear the screen. So move clearing the screen to creator_clear() were it hopefully belongs. - Properly implement V_DISPLAY_BLANK, V_DISPLAY_STAND_BY and V_DISPLAY_SUSPEND. This makes blank_saver.ko and green_saver.ko work. [1] - Change the order of operations in creator_fill_rect(), i.e. write y before x and cy before cx. This fixes drawing the top part of the border with Elite3D cards when switching from Xorg to a VTY. - Move setting the chip configuration we use and invalidating the cache variables to creator_set_mode() and set the V_ADP_MODECHANGE flag. This causes creator_set_mode() to be called when the X server shuts down which fixes the screen corruption caused most of the time by Xorg not restoring the original configuration present at startup. Inspired by/based on: Xorg [1] Approved by: re (scottl)
247 lines
9.0 KiB
C
247 lines
9.0 KiB
C
/*-
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* Copyright (C) 2000 David S. Miller (davem@redhat.com)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* DAVID MILLER BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* from: XFree86: ffb_dac.h,v 1.1 2000/05/23 04:47:44 dawes Exp
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*/
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/*-
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* Copyright (c) 2003 Jake Burkholder.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_FB_CREATOR_H_
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#define _DEV_FB_CREATOR_H_
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#define FFB_NREG 24
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#define FFB_DAC 1
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#define FFB_DAC_TYPE 0x0
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#define FFB_DAC_VALUE 0x4
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#define FFB_DAC_TYPE2 0x8
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#define FFB_DAC_VALUE2 0xc
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/* FFB_DAC_TYPE configuration and palette register addresses */
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#define FFB_DAC_CFG_UCTRL 0x1001 /* User Control */
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#define FFB_DAC_CFG_TGEN 0x6000 /* Timing Generator Control */
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#define FFB_DAC_CFG_DID 0x8000 /* Device Identification */
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/* FFB_DAC_CFG_UCTRL register */
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#define FFB_DAC_UCTRL_IPDISAB 0x0001 /* Input Pullup Resistor Dis. */
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#define FFB_DAC_UCTRL_ABLANK 0x0002 /* Asynchronous Blank */
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#define FFB_DAC_UCTRL_DBENAB 0x0004 /* Double-Buffer Enable */
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#define FFB_DAC_UCTRL_OVENAB 0x0008 /* Overlay Enable */
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#define FFB_DAC_UCTRL_WMODE 0x0030 /* Window Mode */
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#define FFB_DAC_UCTRL_WM_COMB 0x0000 /* Window Mode Combined */
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#define FFB_DAC_UCTRL_WM_S4 0x0010 /* Window Mode Separate 4 */
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#define FFB_DAC_UCTRL_WM_S8 0x0020 /* Window Mode Separate 8 */
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#define FFB_DAC_UCTRL_WM_RESV 0x0030 /* Window Mode Reserved */
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#define FFB_DAC_UCTRL_MANREV 0x0f00 /* Manufacturing Revision */
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/* FFB_DAC_CFG_TGEN register */
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#define FFB_DAC_CFG_TGEN_VIDE 0x01 /* Video Enable */
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#define FFB_DAC_CFG_TGEN_TGE 0x02 /* Timing Generator Enable */
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#define FFB_DAC_CFG_TGEN_HSD 0x04 /* HSYNC* Disable */
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#define FFB_DAC_CFG_TGEN_VSD 0x08 /* VSYNC* Disable */
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#define FFB_DAC_CFG_TGEN_EQD 0x10 /* Equalization Disable */
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#define FFB_DAC_CFG_TGEN_MM 0x20 /* 0 = Slave, 1 = Master */
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#define FFB_DAC_CFG_TGEN_IM 0x40 /* 1 = Interlaced Mode */
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/* FFB_DAC_CFG_DID register */
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#define FFB_DAC_CFG_DID_ONE 0x00000001 /* Always Set */
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#define FFB_DAC_CFG_DID_MANUF 0x00000ffe /* DAC Manufacturer ID */
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#define FFB_DAC_CFG_DID_PNUM 0x0ffff000 /* DAC Part Number */
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#define FFB_DAC_CFG_DID_REV 0xf0000000 /* DAC Revision */
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/* FFB_DAC_TYPE2 cursor register addresses */
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#define FFB_DAC_CUR_BITMAP_P0 0x0 /* Plane 0 Cursor Bitmap */
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#define FFB_DAC_CUR_BITMAP_P1 0x80 /* Plane 1 Cursor Bitmap */
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#define FFB_DAC_CUR_CTRL 0x100 /* Cursor Control */
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#define FFB_DAC_CUR_COLOR0 0x101 /* Cursor Color 0 */
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#define FFB_DAC_CUR_COLOR1 0x102 /* Cursor Color 1 (bg) */
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#define FFB_DAC_CUR_COLOR2 0x103 /* Cursor Color 2 (fg) */
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#define FFB_DAC_CUR_POS 0x104 /* Active Cursor Position */
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/* FFB_DAC_CUR_CTRL register (might be inverted on PAC1 DACs) */
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#define FFB_DAC_CUR_CTRL_P0 0x1 /* Plane0 Display Disable */
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#define FFB_DAC_CUR_CTRL_P1 0x2 /* Plane1 Display Disable */
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#define FFB_FBC 2
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#define FFB_FBC_BY 0x60
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#define FFB_FBC_BX 0x64
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#define FFB_FBC_DY 0x68
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#define FFB_FBC_DX 0x6c
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#define FFB_FBC_BH 0x70
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#define FFB_FBC_BW 0x74
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#define FFB_FBC_PPC 0x200 /* Pixel Processor Control */
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#define FFB_FBC_FG 0x208 /* Foreground */
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#define FFB_FBC_BG 0x20c /* Background */
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#define FFB_FBC_FBC 0x254 /* Frame Buffer Control */
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#define FFB_FBC_ROP 0x258 /* Raster Operation */
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#define FFB_FBC_PMASK 0x290 /* Pixel Mask */
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#define FFB_FBC_DRAWOP 0x300 /* Draw Operation */
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#define FFB_FBC_FONTXY 0x314 /* Font X/Y */
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#define FFB_FBC_FONTW 0x318 /* Font Width */
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#define FFB_FBC_FONTINC 0x31c /* Font Increment */
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#define FFB_FBC_FONT 0x320 /* Font Data */
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#define FFB_FBC_UCSR 0x900 /* User Control & Status */
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#define FBC_PPC_VCE_DIS 0x00001000
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#define FBC_PPC_APE_DIS 0x00000800
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#define FBC_PPC_TBE_OPAQUE 0x00000200
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#define FBC_PPC_CS_CONST 0x00000003
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#define FFB_FBC_WB_A 0x20000000
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#define FFB_FBC_RB_A 0x00004000
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#define FFB_FBC_SB_BOTH 0x00003000
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#define FFB_FBC_XE_OFF 0x00000040
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#define FFB_FBC_RGBE_MASK 0x0000003f
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#define FBC_ROP_NEW 0x83
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#define FBC_DRAWOP_RECTANGLE 0x08
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#define FBC_UCSR_FIFO_OVFL 0x80000000
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#define FBC_UCSR_READ_ERR 0x40000000
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#define FBC_UCSR_RP_BUSY 0x02000000
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#define FBC_UCSR_FB_BUSY 0x01000000
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#define FBC_UCSR_FIFO_MASK 0x00000fff
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#define FFB_VIRT_SFB8R 0x00000000
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#define FFB_VIRT_SFB8G 0x00400000
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#define FFB_VIRT_SFB8B 0x00800000
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#define FFB_VIRT_SFB8X 0x00c00000
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#define FFB_VIRT_SFB32 0x01000000
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#define FFB_VIRT_SFB64 0x02000000
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#define FFB_VIRT_FBC 0x04000000
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#define FFB_VIRT_FBC_BM 0x04002000
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#define FFB_VIRT_DFB8R 0x04004000
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#define FFB_VIRT_DFB8G 0x04404000
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#define FFB_VIRT_DFB8B 0x04804000
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#define FFB_VIRT_DFB8X 0x04c04000
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#define FFB_VIRT_DFB24 0x05004000
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#define FFB_VIRT_DFB32 0x06004000
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#define FFB_VIRT_DFB422A 0x07004000
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#define FFB_VIRT_DFB422AD 0x07804000
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#define FFB_VIRT_DFB24B 0x08004000
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#define FFB_VIRT_DFB422B 0x09004000
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#define FFB_VIRT_DFB422BD 0x09804000
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#define FFB_VIRT_SFB16Z 0x0a004000
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#define FFB_VIRT_SFB8Z 0x0a404000
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#define FFB_VIRT_SFB422 0x0ac04000
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#define FFB_VIRT_SFB422D 0x0b404000
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#define FFB_VIRT_FBC_KREG 0x0bc04000
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#define FFB_VIRT_DAC 0x0bc06000
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#define FFB_VIRT_PROM 0x0bc08000
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#define FFB_VIRT_EXP 0x0bc18000
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#define FFB_PHYS_SFB8R 0x04000000
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#define FFB_PHYS_SFB8G 0x04400000
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#define FFB_PHYS_SFB8B 0x04800000
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#define FFB_PHYS_SFB8X 0x04c00000
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#define FFB_PHYS_SFB32 0x05000000
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#define FFB_PHYS_SFB64 0x06000000
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#define FFB_PHYS_FBC 0x00600000
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#define FFB_PHYS_FBC_BM 0x00600000
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#define FFB_PHYS_DFB8R 0x01000000
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#define FFB_PHYS_DFB8G 0x01400000
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#define FFB_PHYS_DFB8B 0x01800000
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#define FFB_PHYS_DFB8X 0x01c00000
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#define FFB_PHYS_DFB24 0x02000000
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#define FFB_PHYS_DFB32 0x03000000
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#define FFB_PHYS_DFB422A 0x09000000
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#define FFB_PHYS_DFB422AD 0x09800000
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#define FFB_PHYS_DFB24B 0x0a000000
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#define FFB_PHYS_DFB422B 0x0b000000
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#define FFB_PHYS_DFB422BD 0x0b800000
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#define FFB_PHYS_SFB16Z 0x0c800000
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#define FFB_PHYS_SFB8Z 0x0c000000
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#define FFB_PHYS_SFB422 0x0d000000
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#define FFB_PHYS_SFB422D 0x0d800000
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#define FFB_PHYS_FBC_KREG 0x00610000
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#define FFB_PHYS_DAC 0x00400000
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#define FFB_PHYS_PROM 0x00000000
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#define FFB_PHYS_EXP 0x00200000
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#define FFB_READ(sc, reg, off) \
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bus_space_read_4((sc)->sc_bt[(reg)], (sc)->sc_bh[(reg)], (off))
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#define FFB_WRITE(sc, reg, off, val) \
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bus_space_write_4((sc)->sc_bt[(reg)], (sc)->sc_bh[(reg)], (off), (val))
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#define CREATOR_DRIVER_NAME "creator"
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struct creator_softc {
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video_adapter_t sc_va; /* XXX must be first */
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phandle_t sc_node;
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struct cdev *sc_si;
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int sc_rid[FFB_NREG];
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struct resource *sc_reg[FFB_NREG];
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bus_space_tag_t sc_bt[FFB_NREG];
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bus_space_handle_t sc_bh[FFB_NREG];
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int sc_height;
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int sc_width;
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int sc_xmargin;
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int sc_ymargin;
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u_char *sc_font;
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int sc_bg_cache;
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int sc_fg_cache;
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int sc_fifo_cache;
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int sc_fontinc_cache;
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int sc_fontw_cache;
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int sc_pmask_cache;
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int sc_flags;
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#define CREATOR_AFB (1 << 0)
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#define CREATOR_CONSOLE (1 << 1)
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#define CREATOR_CUREN (1 << 2)
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#define CREATOR_CURINV (1 << 3)
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#define CREATOR_PAC1 (1 << 4)
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};
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#endif /* !_DEV_FB_CREATOR_H_ */
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