6d2d7b8c0d
already supported nested PICs, but was limited to having a nested
AT-PIC only. With G5 support the need for nested OpenPIC controllers
needed to be added. This was done the wrong way and broke the MPC8555
eval system in the process.
OFW, as well as FDT, describe the interrupt routing in terms of a
controller and an interrupt pin on it. This needs to be mapped to a
flat and global resource: the IRQ. The IRQ is the same as the PCI
intline and as such needs to be representable in 8 bits. Secondly,
ISA support pretty much dictates that IRQ 0-15 should be reserved
for ISA interrupts, because of the internal workins of south bridges.
Both were broken.
This change reverts revision 209298 for a big part and re-implements
it simpler. In particular:
o The id() method of the PIC I/F is removed again. It's not needed.
o The openpic_attach() function has been changed to take the OFW
or FDT phandle of the controller as a second argument. All bus
attachments that previously used openpic_attach() as the attach
method of the device I/F now implement as bus-specific method
and pass the phandle_t to the renamed openpic_attach().
o Change powerpc_register_pic() to take a few more arguments. In
particular:
- Pass the number of IPIs specificly. The number of IRQs carved
out for a PIC is the sum of the number of int. pins and IPIs.
- Pass a flag indicating whether the PIC is an AT-PIC or not.
This tells the interrupt framework whether to assign IRQ 0-15
or some other range.
o Until we implement proper multi-pass bus enumeration, we have to
handle the case where we need to map from PIC+pin to IRQ *before*
the PIC gets registered. This is done in a similar way as before,
but rather than carving out 256 IRQs per PIC, we carve out 128
IRQs (124 pins + 4 IPIs). This is supposed to handle the G5 case,
but should really be fixed properly using multiple passes.
o Have the interrupt framework set root_pic in most cases and not
put that burden in PIC drivers (for the most part).
o Remove powerpc_ign_lookup() and replace it with powerpc_get_irq().
Remove IGN_SHIFT, INTR_INTLINE and INTR_IGN.
Related to the above, fix the Freescale PCI controller driver, broken
by the FDT code. Besides not attaching properly, bus numbers were
assigned improperly and enumeration was broken in general. This
prevented the AT PIC from being discovered and interrupt routing to
work properly. Consequently, the ata(4) controller stopped functioning.
Fix the driver, and FDT PCI support, enough to get the MPC8555CDS
going again. The FDT PCI code needs a whole lot more work.
No breakages are expected, but lackiong G5 hardware, it's possible
that there are unpleasant side-effects. At least MPC85xx support is
back to where it was 7 months ago -- it's amazing how badly support
can be broken in just 7 months...
Sponsored by: Juniper Networks
328 lines
8.0 KiB
C
328 lines
8.0 KiB
C
/*-
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* Copyright (c) 2009 Marcel Moolenaar
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <machine/intr_machdep.h>
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#include <machine/pio.h>
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#include <powerpc/mpc85xx/mpc85xx.h>
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#include <dev/ic/i8259.h>
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#include <isa/isareg.h>
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#include <isa/isavar.h>
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#include "pic_if.h"
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#define ATPIC_MASTER 0
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#define ATPIC_SLAVE 1
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struct atpic_softc {
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device_t sc_dev;
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/* I/O port resources for master & slave. */
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struct resource *sc_res[2];
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int sc_rid[2];
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/* Our "routing" interrupt */
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struct resource *sc_ires;
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void *sc_icookie;
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int sc_irid;
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int sc_vector[16];
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uint8_t sc_mask[2];
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};
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static int atpic_isa_attach(device_t);
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static void atpic_isa_identify(driver_t *, device_t);
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static int atpic_isa_probe(device_t);
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static void atpic_config(device_t, u_int, enum intr_trigger,
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enum intr_polarity);
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static void atpic_dispatch(device_t, struct trapframe *);
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static void atpic_enable(device_t, u_int, u_int);
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static void atpic_eoi(device_t, u_int);
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static void atpic_ipi(device_t, u_int);
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static void atpic_mask(device_t, u_int);
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static void atpic_unmask(device_t, u_int);
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static device_method_t atpic_isa_methods[] = {
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/* Device interface */
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DEVMETHOD(device_identify, atpic_isa_identify),
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DEVMETHOD(device_probe, atpic_isa_probe),
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DEVMETHOD(device_attach, atpic_isa_attach),
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/* PIC interface */
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DEVMETHOD(pic_config, atpic_config),
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DEVMETHOD(pic_dispatch, atpic_dispatch),
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DEVMETHOD(pic_enable, atpic_enable),
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DEVMETHOD(pic_eoi, atpic_eoi),
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DEVMETHOD(pic_ipi, atpic_ipi),
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DEVMETHOD(pic_mask, atpic_mask),
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DEVMETHOD(pic_unmask, atpic_unmask),
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{ 0, 0 },
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};
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static driver_t atpic_isa_driver = {
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"atpic",
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atpic_isa_methods,
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sizeof(struct atpic_softc)
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};
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static devclass_t atpic_devclass;
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DRIVER_MODULE(atpic, isa, atpic_isa_driver, atpic_devclass, 0, 0);
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static struct isa_pnp_id atpic_ids[] = {
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{ 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
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{ 0 }
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};
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static __inline uint8_t
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atpic_read(struct atpic_softc *sc, int icu, int ofs)
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{
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uint8_t val;
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val = bus_read_1(sc->sc_res[icu], ofs);
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return (val);
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}
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static __inline void
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atpic_write(struct atpic_softc *sc, int icu, int ofs, uint8_t val)
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{
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bus_write_1(sc->sc_res[icu], ofs, val);
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bus_barrier(sc->sc_res[icu], ofs, 2 - ofs,
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BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
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}
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static void
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atpic_intr(void *arg)
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{
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atpic_dispatch(arg, NULL);
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}
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static void
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atpic_isa_identify(driver_t *drv, device_t parent)
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{
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device_t child;
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child = BUS_ADD_CHILD(parent, ISA_ORDER_SENSITIVE, drv->name, -1);
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device_set_driver(child, drv);
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isa_set_logicalid(child, atpic_ids[0].ip_id);
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isa_set_vendorid(child, atpic_ids[0].ip_id);
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bus_set_resource(child, SYS_RES_IOPORT, ATPIC_MASTER, IO_ICU1, 2);
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bus_set_resource(child, SYS_RES_IOPORT, ATPIC_SLAVE, IO_ICU2, 2);
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/* ISA interrupts are routed through external interrupt 0. */
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bus_set_resource(child, SYS_RES_IRQ, 0, 16, 1);
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}
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static int
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atpic_isa_probe(device_t dev)
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{
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int res;
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res = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids);
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if (res > 0)
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return (res);
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device_set_desc(dev, "PC/AT compatible PIC");
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return (res);
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}
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static void
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atpic_init(struct atpic_softc *sc, int icu)
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{
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sc->sc_mask[icu] = 0xff - ((icu == ATPIC_MASTER) ? 4 : 0);
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atpic_write(sc, icu, 0, ICW1_RESET | ICW1_IC4);
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atpic_write(sc, icu, 1, (icu == ATPIC_SLAVE) ? 8 : 0);
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atpic_write(sc, icu, 1, (icu == ATPIC_SLAVE) ? 2 : 4);
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atpic_write(sc, icu, 1, ICW4_8086);
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atpic_write(sc, icu, 1, sc->sc_mask[icu]);
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atpic_write(sc, icu, 0, OCW3_SEL | OCW3_RR);
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}
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static int
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atpic_isa_attach(device_t dev)
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{
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struct atpic_softc *sc;
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int error;
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sc = device_get_softc(dev);
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sc->sc_dev = dev;
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error = ENXIO;
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sc->sc_rid[ATPIC_MASTER] = 0;
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sc->sc_res[ATPIC_MASTER] = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
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&sc->sc_rid[ATPIC_MASTER], RF_ACTIVE);
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if (sc->sc_res[ATPIC_MASTER] == NULL)
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goto fail;
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sc->sc_rid[ATPIC_SLAVE] = 1;
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sc->sc_res[ATPIC_SLAVE] = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
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&sc->sc_rid[ATPIC_SLAVE], RF_ACTIVE);
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if (sc->sc_res[ATPIC_SLAVE] == NULL)
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goto fail;
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sc->sc_irid = 0;
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sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irid,
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RF_ACTIVE);
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if (sc->sc_ires == NULL)
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goto fail;
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error = bus_setup_intr(dev, sc->sc_ires, INTR_TYPE_MISC | INTR_MPSAFE,
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NULL, atpic_intr, dev, &sc->sc_icookie);
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if (error)
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goto fail;
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atpic_init(sc, ATPIC_SLAVE);
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atpic_init(sc, ATPIC_MASTER);
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powerpc_register_pic(dev, 0, 16, 0, TRUE);
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return (0);
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fail:
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if (sc->sc_ires != NULL)
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bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid,
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sc->sc_ires);
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if (sc->sc_res[ATPIC_SLAVE] != NULL)
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bus_release_resource(dev, SYS_RES_IOPORT,
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sc->sc_rid[ATPIC_SLAVE], sc->sc_res[ATPIC_SLAVE]);
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if (sc->sc_res[ATPIC_MASTER] != NULL)
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bus_release_resource(dev, SYS_RES_IOPORT,
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sc->sc_rid[ATPIC_MASTER], sc->sc_res[ATPIC_MASTER]);
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return (error);
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}
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/*
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* PIC interface.
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*/
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static void
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atpic_config(device_t dev, u_int irq, enum intr_trigger trig,
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enum intr_polarity pol)
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{
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}
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static void
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atpic_dispatch(device_t dev, struct trapframe *tf)
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{
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struct atpic_softc *sc;
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uint8_t irq;
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sc = device_get_softc(dev);
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atpic_write(sc, ATPIC_MASTER, 0, OCW3_SEL | OCW3_P);
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irq = atpic_read(sc, ATPIC_MASTER, 0);
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atpic_write(sc, ATPIC_MASTER, 0, OCW3_SEL | OCW3_RR);
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if ((irq & 0x80) == 0)
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return;
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if (irq == 0x82) {
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atpic_write(sc, ATPIC_SLAVE, 0, OCW3_SEL | OCW3_P);
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irq = atpic_read(sc, ATPIC_SLAVE, 0) + 8;
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atpic_write(sc, ATPIC_SLAVE, 0, OCW3_SEL | OCW3_RR);
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if ((irq & 0x80) == 0)
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return;
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}
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powerpc_dispatch_intr(sc->sc_vector[irq & 0x0f], tf);
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}
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static void
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atpic_enable(device_t dev, u_int irq, u_int vector)
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{
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struct atpic_softc *sc;
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sc = device_get_softc(dev);
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sc->sc_vector[irq] = vector;
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atpic_unmask(dev, irq);
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}
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static void
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atpic_eoi(device_t dev, u_int irq)
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{
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struct atpic_softc *sc;
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sc = device_get_softc(dev);
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if (irq > 7)
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atpic_write(sc, ATPIC_SLAVE, 0, OCW2_EOI);
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atpic_write(sc, ATPIC_MASTER, 0, OCW2_EOI);
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}
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static void
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atpic_ipi(device_t dev, u_int cpu)
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{
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/* No SMP support. */
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}
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static void
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atpic_mask(device_t dev, u_int irq)
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{
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struct atpic_softc *sc;
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sc = device_get_softc(dev);
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if (irq > 7) {
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sc->sc_mask[ATPIC_SLAVE] |= 1 << (irq - 8);
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atpic_write(sc, ATPIC_SLAVE, 1, sc->sc_mask[ATPIC_SLAVE]);
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} else {
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sc->sc_mask[ATPIC_MASTER] |= 1 << irq;
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atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]);
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}
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}
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static void
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atpic_unmask(device_t dev, u_int irq)
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{
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struct atpic_softc *sc;
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sc = device_get_softc(dev);
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if (irq > 7) {
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sc->sc_mask[ATPIC_SLAVE] &= ~(1 << (irq - 8));
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atpic_write(sc, ATPIC_SLAVE, 1, sc->sc_mask[ATPIC_SLAVE]);
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} else {
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sc->sc_mask[ATPIC_MASTER] &= ~(1 << irq);
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atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]);
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}
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}
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