freebsd-dev/sys/riscv
Mitchell Horne 9b4cbaa9c3 riscv: handle misaligned address exceptions
If this exception is coming from userspace, send the appropriate SIGBUS
to the process. If it's coming from the kernel this is still fatal, but
we can give a better panic message.

Typical misaligned loads/stores are emulated by the SBI firmware, and
require no intervention from our kernel. The notable exception here is
misaligned access with atomic instructions. These can generate the
exception and panic seen in the PR.

With this, we now handle all defined exception types.

PR:		266109
MFC after:	1 week
Found by:	syzkaller
Reported by:	P1umer <p1umer1337@gmail.com>
Differential Revision:	https://reviews.freebsd.org/D36876
2022-10-11 10:39:50 -03:00
..
allwinner aw_wdog: support Allwinner D1 watchdog 2022-04-12 19:51:17 -03:00
conf Sync TCP related kernel config options 2022-10-10 15:40:26 +02:00
include sys: Consolidate common implementation details of PV entries. 2022-10-07 10:14:03 -07:00
riscv riscv: handle misaligned address exceptions 2022-10-11 10:39:50 -03:00
sifive riscv sifive: Remove unused devclass arguments to DRIVER_MODULE. 2022-05-10 10:21:38 -07:00