d20841648d
locking, and the apparently unnecessary locking for -stable has been removed. This may fix issues with missed interrupts since April, which manifested themselves as slowdowns or hangs in radeon, in particular. Many cleanups also took place. In the shared code, there are improvements to r128 driver stability.
261 lines
6.9 KiB
C
261 lines
6.9 KiB
C
/* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*-
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*
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* Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
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*
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* The Weather Channel (TM) funded Tungsten Graphics to develop the
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* initial release of the Radeon 8500 driver under the XFree86 license.
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* This notice must be preserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Keith Whitwell <keith@tungstengraphics.com>
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* Michel Dänzer <michel@daenzer.net>
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*
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* $FreeBSD$
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*/
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#include "dev/drm/radeon.h"
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#include "dev/drm/drmP.h"
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#include "dev/drm/drm.h"
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#include "dev/drm/radeon_drm.h"
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#include "dev/drm/radeon_drv.h"
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/* Interrupts - Used for device synchronization and flushing in the
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* following circumstances:
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*
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* - Exclusive FB access with hw idle:
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* - Wait for GUI Idle (?) interrupt, then do normal flush.
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*
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* - Frame throttling, NV_fence:
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* - Drop marker irq's into command stream ahead of time.
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* - Wait on irq's with lock *not held*
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* - Check each for termination condition
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*
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* - Internally in cp_getbuffer, etc:
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* - as above, but wait with lock held???
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*
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* NOTE: These functions are misleadingly named -- the irq's aren't
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* tied to dma at all, this is just a hangover from dri prehistory.
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*/
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irqreturn_t DRM(irq_handler)( DRM_IRQ_ARGS )
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{
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drm_device_t *dev = (drm_device_t *) arg;
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drm_radeon_private_t *dev_priv =
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(drm_radeon_private_t *)dev->dev_private;
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u32 stat;
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/* Only consider the bits we're interested in - others could be used
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* outside the DRM
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*/
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stat = RADEON_READ(RADEON_GEN_INT_STATUS)
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& (RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT);
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if (!stat)
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return IRQ_NONE;
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/* SW interrupt */
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if (stat & RADEON_SW_INT_TEST) {
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DRM_WAKEUP( &dev_priv->swi_queue );
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}
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/* VBLANK interrupt */
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if (stat & RADEON_CRTC_VBLANK_STAT) {
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atomic_inc(&dev->vbl_received);
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DRM_WAKEUP(&dev->vbl_queue);
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DRM(vbl_send_signals)( dev );
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}
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/* Acknowledge interrupts we handle */
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RADEON_WRITE(RADEON_GEN_INT_STATUS, stat);
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return IRQ_HANDLED;
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}
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static __inline__ void radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv)
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{
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u32 tmp = RADEON_READ( RADEON_GEN_INT_STATUS )
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& (RADEON_SW_INT_TEST_ACK | RADEON_CRTC_VBLANK_STAT);
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if (tmp)
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RADEON_WRITE( RADEON_GEN_INT_STATUS, tmp );
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}
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int radeon_emit_irq(drm_device_t *dev)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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unsigned int ret;
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RING_LOCALS;
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atomic_inc(&dev_priv->swi_emitted);
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ret = atomic_read(&dev_priv->swi_emitted);
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BEGIN_RING( 4 );
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OUT_RING_REG( RADEON_LAST_SWI_REG, ret );
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OUT_RING_REG( RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE );
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ADVANCE_RING();
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COMMIT_RING();
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return ret;
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}
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int radeon_wait_irq(drm_device_t *dev, int swi_nr)
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{
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drm_radeon_private_t *dev_priv =
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(drm_radeon_private_t *)dev->dev_private;
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int ret = 0;
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if (RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr)
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return 0;
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dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
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/* This is a hack to work around mysterious freezes on certain
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* systems:
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*/
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radeon_acknowledge_irqs( dev_priv );
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DRM_WAIT_ON( ret, dev_priv->swi_queue, 3 * DRM_HZ,
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RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr );
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return ret;
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}
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int radeon_emit_and_wait_irq(drm_device_t *dev)
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{
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return radeon_wait_irq( dev, radeon_emit_irq(dev) );
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}
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int DRM(vblank_wait)(drm_device_t *dev, unsigned int *sequence)
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{
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drm_radeon_private_t *dev_priv =
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(drm_radeon_private_t *)dev->dev_private;
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unsigned int cur_vblank;
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int ret = 0;
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if ( !dev_priv ) {
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DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
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return DRM_ERR(EINVAL);
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}
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radeon_acknowledge_irqs( dev_priv );
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dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
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/* Assume that the user has missed the current sequence number
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* by about a day rather than she wants to wait for years
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* using vertical blanks...
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*/
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DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ,
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( ( ( cur_vblank = atomic_read(&dev->vbl_received ) )
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- *sequence ) <= (1<<23) ) );
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*sequence = cur_vblank;
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return ret;
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}
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/* Needs the lock as it touches the ring.
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*/
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int radeon_irq_emit( DRM_IOCTL_ARGS )
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{
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DRM_DEVICE;
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_radeon_irq_emit_t emit;
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int result;
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LOCK_TEST_WITH_RETURN( dev, filp );
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if ( !dev_priv ) {
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DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
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return DRM_ERR(EINVAL);
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}
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DRM_COPY_FROM_USER_IOCTL( emit, (drm_radeon_irq_emit_t *)data,
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sizeof(emit) );
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result = radeon_emit_irq( dev );
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if ( DRM_COPY_TO_USER( emit.irq_seq, &result, sizeof(int) ) ) {
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DRM_ERROR( "copy_to_user\n" );
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return DRM_ERR(EFAULT);
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}
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return 0;
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}
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/* Doesn't need the hardware lock.
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*/
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int radeon_irq_wait( DRM_IOCTL_ARGS )
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{
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DRM_DEVICE;
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_radeon_irq_wait_t irqwait;
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if ( !dev_priv ) {
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DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
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return DRM_ERR(EINVAL);
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}
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DRM_COPY_FROM_USER_IOCTL( irqwait, (drm_radeon_irq_wait_t *)data,
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sizeof(irqwait) );
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return radeon_wait_irq( dev, irqwait.irq_seq );
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}
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/* drm_dma.h hooks
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*/
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void DRM(driver_irq_preinstall)( drm_device_t *dev ) {
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drm_radeon_private_t *dev_priv =
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(drm_radeon_private_t *)dev->dev_private;
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/* Disable *all* interrupts */
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RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
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/* Clear bits if they're already high */
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radeon_acknowledge_irqs( dev_priv );
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}
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void DRM(driver_irq_postinstall)( drm_device_t *dev ) {
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drm_radeon_private_t *dev_priv =
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(drm_radeon_private_t *)dev->dev_private;
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atomic_set(&dev_priv->swi_emitted, 0);
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DRM_INIT_WAITQUEUE( &dev_priv->swi_queue );
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/* Turn on SW and VBL ints */
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RADEON_WRITE( RADEON_GEN_INT_CNTL,
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RADEON_CRTC_VBLANK_MASK |
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RADEON_SW_INT_ENABLE );
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}
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void DRM(driver_irq_uninstall)( drm_device_t *dev ) {
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drm_radeon_private_t *dev_priv =
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(drm_radeon_private_t *)dev->dev_private;
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if (!dev_priv)
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return;
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/* Disable *all* interrupts */
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RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
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}
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