9f499cc5ae
The changes are: - the microcore code loaded into the NAE has to be byteswapped in LE - the descriptors in memory for a P2P NAE descriptor has to be byteswapped in LE - the m_data pointer is already cacheline aligned, so the unnecessary m_adj to cacheline size can be removed - fix mask used to obtain physical address from the Tx freeback descriptor - fix a compile error in code under #ifdef Obtained from: Venkatesh J V <venkatesh.vivekanandan@broadcom.com>
142 lines
4.2 KiB
C
142 lines
4.2 KiB
C
/*-
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __NLM_UCORE_LOADER_H__
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#define __NLM_UCORE_LOADER_H__
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/**
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* @file_name ucore_loader.h
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* @author Netlogic Microsystems
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* @brief Ucore loader API header
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*/
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#define CODE_SIZE_PER_UCORE (4 << 10)
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static __inline__ void
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nlm_ucore_load_image(uint64_t nae_base, int ucore)
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{
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uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET +
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(ucore * CODE_SIZE_PER_UCORE);
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uint32_t *p = (uint32_t *)ucore_app_bin;
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int i, size;
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size = sizeof(ucore_app_bin)/sizeof(uint32_t);
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for (i = 0; i < size; i++, addr += 4)
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nlm_store_word_daddr(addr, htobe32(p[i]));
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/* add a 'nop' if number of instructions are odd */
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if (size & 0x1)
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nlm_store_word_daddr(addr, 0x0);
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}
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static __inline int
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nlm_ucore_write_sharedmem(uint64_t nae_base, int index, uint32_t data)
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{
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uint32_t ucore_cfg;
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uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET;
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if (index > 128)
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return (-1);
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ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
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/* set iram to zero */
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nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG,
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(ucore_cfg & ~(0x1 << 7)));
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nlm_store_word_daddr(addr + (index * 4), data);
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/* restore ucore config */
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nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);
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return (0);
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}
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static __inline uint32_t
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nlm_ucore_read_sharedmem(uint64_t nae_base, int index)
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{
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uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET;
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uint32_t ucore_cfg, val;
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ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
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/* set iram to zero */
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nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG,
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(ucore_cfg & ~(0x1 << 7)));
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val = nlm_load_word_daddr(addr + (index * 4));
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/* restore ucore config */
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nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);
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return val;
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}
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static __inline__ int
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nlm_ucore_load_all(uint64_t nae_base, uint32_t ucore_mask, int nae_reset_done)
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{
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int i, count = 0;
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uint32_t mask;
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uint32_t ucore_cfg = 0;
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mask = ucore_mask & 0xffff;
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/* Stop all ucores */
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if (nae_reset_done == 0) { /* Skip the Ucore reset if NAE reset is done */
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ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
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nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG,
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ucore_cfg | (1 << 24));
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/* poll for ucore to get in to a wait state */
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do {
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ucore_cfg = nlm_read_nae_reg(nae_base,
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NAE_RX_UCORE_CFG);
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} while ((ucore_cfg & (1 << 25)) == 0);
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}
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for (i = 0; i < sizeof(ucore_mask) * NBBY; i++) {
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if ((mask & (1 << i)) == 0)
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continue;
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nlm_ucore_load_image(nae_base, i);
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count++;
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}
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/* Enable per-domain ucores */
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ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
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/* write one to reset bits to put the ucores in reset */
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ucore_cfg = ucore_cfg | (((mask) & 0xffff) << 8);
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nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);
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/* write zero to reset bits to pull them out of reset */
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ucore_cfg = ucore_cfg & (~(((mask) & 0xffff) << 8)) & ~(1 << 24);
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nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);
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return (count);
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}
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#endif
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