34da911965
Re-write tlb operations in C with a simpler API. Update callers to use the new API. Changes from http://svn.freebsd.org/base/user/jmallett/octeon Approved by: rrs(mentor), jmallett
130 lines
5.0 KiB
C
130 lines
5.0 KiB
C
/*-
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* Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PTE_H_
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#define _MACHINE_PTE_H_
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/*
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* TLB and PTE management. Most things operate within the context of
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* EntryLo0,1, and begin with TLBLO_. Things which work with EntryHi
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* start with TLBHI_. PTE bits begin with PG_.
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*
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* Note that we use the same size VM and TLB pages.
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*/
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#define TLB_PAGE_SHIFT (PAGE_SHIFT)
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#define TLB_PAGE_SIZE (1 << TLB_PAGE_SHIFT)
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#define TLB_PAGE_MASK (TLB_PAGE_SIZE - 1)
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/*
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* TLB PageMask register. Has mask bits set above the default, 4K, page mask.
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*/
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#define TLBMASK_SHIFT (13)
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#define TLBMASK_MASK ((PAGE_MASK >> TLBMASK_SHIFT) << TLBMASK_SHIFT)
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/*
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* PFN for EntryLo register. Upper bits are 0, which is to say that
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* bit 29 is the last hardware bit; Bits 30 and upwards (EntryLo is
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* 64 bit though it can be referred to in 32-bits providing 2 software
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* bits safely. We use it as 64 bits to get many software bits, and
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* god knows what else.) are unacknowledged by hardware. They may be
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* written as anything, but otherwise they have as much meaning as
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* other 0 fields.
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*/
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#define TLBLO_SWBITS_SHIFT (30)
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#define TLBLO_SWBITS_MASK (0x3U << TLBLO_SWBITS_SHIFT)
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#define TLBLO_PFN_SHIFT (6)
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#define TLBLO_PFN_MASK (0x3FFFFFC0)
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#define TLBLO_PA_TO_PFN(pa) ((((pa) >> TLB_PAGE_SHIFT) << TLBLO_PFN_SHIFT) & TLBLO_PFN_MASK)
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#define TLBLO_PFN_TO_PA(pfn) ((vm_paddr_t)((pfn) >> TLBLO_PFN_SHIFT) << TLB_PAGE_SHIFT)
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#define TLBLO_PTE_TO_PFN(pte) ((pte) & TLBLO_PFN_MASK)
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#define TLBLO_PTE_TO_PA(pte) (TLBLO_PFN_TO_PA(TLBLO_PTE_TO_PFN((pte))))
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/*
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* VPN for EntryHi register. Upper two bits select user, supervisor,
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* or kernel. Bits 61 to 40 copy bit 63. VPN2 is bits 39 and down to
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* as low as 13, down to PAGE_SHIFT, to index 2 TLB pages*. From bit 12
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* to bit 8 there is a 5-bit 0 field. Low byte is ASID.
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*
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* Note that in FreeBSD, we map 2 TLB pages is equal to 1 VM page.
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*/
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#define TLBHI_ASID_MASK (0xff)
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#define TLBHI_ENTRY(va, asid) (((va) & ~PAGE_MASK) | ((asid) & TLBHI_ASID_MASK))
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#ifndef _LOCORE
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typedef unsigned int pt_entry_t;
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typedef pt_entry_t *pd_entry_t;
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#endif
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#define PDESIZE sizeof(pd_entry_t) /* for assembly files */
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#define PTESIZE sizeof(pt_entry_t) /* for assembly files */
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#define PT_ENTRY_NULL ((pt_entry_t *) 0)
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#define PTE_WIRED 0x80000000 /* SW */
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#define PTE_W PTE_WIRED
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#define PTE_RO 0x40000000 /* SW */
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#define PTE_G 0x00000001 /* HW */
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#define PTE_V 0x00000002
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/*#define PTE_NV 0x00000000 Not Used */
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#define PTE_M 0x00000004
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#define PTE_RW PTE_M
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#define PTE_ODDPG 0x00001000
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/*#define PG_ATTR 0x0000003f Not Used */
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#define PTE_UNCACHED 0x00000010
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#ifdef CPU_SB1
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#define PTE_CACHE 0x00000028 /* cacheable coherent */
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#else
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#define PTE_CACHE 0x00000018
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#endif
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/*#define PG_CACHEMODE 0x00000038 Not Used*/
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#define PTE_ROPAGE (PTE_V | PTE_RO | PTE_CACHE) /* Write protected */
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#define PTE_RWPAGE (PTE_V | PTE_M | PTE_CACHE) /* Not wr-prot not clean */
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#define PTE_CWPAGE (PTE_V | PTE_CACHE) /* Not wr-prot but clean */
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#define PTE_IOPAGE (PTE_G | PTE_V | PTE_M | PTE_UNCACHED)
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#define PTE_FRAME 0x3fffffc0
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#define PTE_HVPN 0xffffe000 /* Hardware page no mask */
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#define PTE_ASID 0x000000ff /* Address space ID */
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/* User virtual to pte offset in page table */
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#define vad_to_pte_offset(adr) (((adr) >> PAGE_SHIFT) & (NPTEPG -1))
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#define mips_pg_v(entry) ((entry) & PTE_V)
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#define mips_pg_wired(entry) ((entry) & PTE_WIRED)
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#define mips_pg_m_bit() (PTE_M)
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#define mips_pg_rw_bit() (PTE_M)
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#define mips_pg_ro_bit() (PTE_RO)
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#define mips_pg_ropage_bit() (PTE_ROPAGE)
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#define mips_pg_rwpage_bit() (PTE_RWPAGE)
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#define mips_pg_cwpage_bit() (PTE_CWPAGE)
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#define mips_pg_global_bit() (PTE_G)
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#define mips_pg_wired_bit() (PTE_WIRED)
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#endif /* !_MACHINE_PTE_H_ */
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