Andrew Turner 45951bf0a9 Ignore the SMMUv3 and PMCG interrupt controller in the IORT tables ... When mapping MSI/MSI-X interrupts throught he Arm IORT ACPI tables we may need to ignore an interrupt controller even if it is within the bounds the entry describes. When the SMMUv3 is not using GSIV (non-MSI/MSI-X) interrupts we need to read the defined field. The Performance Monitoring Counter Group always ignores the first table entry. MFC after: 2 weeks Sponsored by: DARPA, AFRL		2020-01-31 09:51:38 +00:00
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acpi_iort.c	Ignore the SMMUv3 and PMCG interrupt controller in the IORT tables	2020-01-31 09:51:38 +00:00
acpi_machdep.c
acpi_wakeup.c
OsdEnvironment.c
pci_cfgreg.c