cafceaebea
EFSCFD (floating point single convert from double) emulation requires saving the high word of the register, which uses SPE instructions. Enable the SPE to avoid an SPV Unavailable exception. MFC after: 1 week
684 lines
16 KiB
C
684 lines
16 KiB
C
/*-
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* Copyright (C) 1996 Wolfgang Solfrank.
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* Copyright (C) 1996 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $NetBSD: fpu.c,v 1.5 2001/07/22 11:29:46 wiz Exp $
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/proc.h>
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#include <sys/systm.h>
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#include <sys/limits.h>
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#include <machine/altivec.h>
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#include <machine/fpu.h>
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#include <machine/ieeefp.h>
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#include <machine/pcb.h>
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#include <machine/psl.h>
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#include <powerpc/fpu/fpu_arith.h>
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#include <powerpc/fpu/fpu_emu.h>
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#include <powerpc/fpu/fpu_extern.h>
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void spe_handle_fpdata(struct trapframe *);
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void spe_handle_fpround(struct trapframe *);
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static int spe_emu_instr(uint32_t, struct fpemu *, struct fpn **, uint32_t *);
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static void
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save_vec_int(struct thread *td)
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{
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int msr;
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struct pcb *pcb;
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pcb = td->td_pcb;
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/*
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* Temporarily re-enable the vector unit during the save
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*/
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msr = mfmsr();
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mtmsr(msr | PSL_VEC);
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/*
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* Save the vector registers and SPEFSCR to the PCB
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*/
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#define EVSTDW(n) __asm ("evstdw %1,0(%0)" \
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:: "b"(pcb->pcb_vec.vr[n]), "n"(n));
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EVSTDW(0); EVSTDW(1); EVSTDW(2); EVSTDW(3);
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EVSTDW(4); EVSTDW(5); EVSTDW(6); EVSTDW(7);
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EVSTDW(8); EVSTDW(9); EVSTDW(10); EVSTDW(11);
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EVSTDW(12); EVSTDW(13); EVSTDW(14); EVSTDW(15);
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EVSTDW(16); EVSTDW(17); EVSTDW(18); EVSTDW(19);
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EVSTDW(20); EVSTDW(21); EVSTDW(22); EVSTDW(23);
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EVSTDW(24); EVSTDW(25); EVSTDW(26); EVSTDW(27);
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EVSTDW(28); EVSTDW(29); EVSTDW(30); EVSTDW(31);
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#undef EVSTDW
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__asm ( "evxor 0,0,0\n"
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"evaddumiaaw 0,0\n"
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"evstdd 0,0(%0)" :: "b"(&pcb->pcb_vec.spare[0]));
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pcb->pcb_vec.vscr = mfspr(SPR_SPEFSCR);
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/*
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* Disable vector unit again
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*/
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isync();
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mtmsr(msr);
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}
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void
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enable_vec(struct thread *td)
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{
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int msr;
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struct pcb *pcb;
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struct trapframe *tf;
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pcb = td->td_pcb;
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tf = trapframe(td);
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/*
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* Save the thread's SPE CPU number, and set the CPU's current
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* vector thread
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*/
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td->td_pcb->pcb_veccpu = PCPU_GET(cpuid);
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PCPU_SET(vecthread, td);
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/*
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* Enable the vector unit for when the thread returns from the
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* exception. If this is the first time the unit has been used by
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* the thread, initialise the vector registers and VSCR to 0, and
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* set the flag to indicate that the vector unit is in use.
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*/
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tf->srr1 |= PSL_VEC;
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if (!(pcb->pcb_flags & PCB_VEC)) {
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memset(&pcb->pcb_vec, 0, sizeof pcb->pcb_vec);
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pcb->pcb_flags |= PCB_VEC;
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pcb->pcb_vec.vscr = mfspr(SPR_SPEFSCR);
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}
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/*
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* Temporarily enable the vector unit so the registers
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* can be restored.
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*/
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msr = mfmsr();
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mtmsr(msr | PSL_VEC);
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/* Restore SPEFSCR and ACC. Use %r0 as the scratch for ACC. */
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mtspr(SPR_SPEFSCR, pcb->pcb_vec.vscr);
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__asm __volatile("evldd 0, 0(%0); evmra 0,0\n"
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:: "b"(&pcb->pcb_vec.spare[0]));
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/*
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* The lower half of each register will be restored on trap return. Use
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* %r0 as a scratch register, and restore it last.
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*/
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#define EVLDW(n) __asm __volatile("evldw 0, 0(%0); evmergehilo "#n",0,"#n \
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:: "b"(&pcb->pcb_vec.vr[n]));
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EVLDW(1); EVLDW(2); EVLDW(3); EVLDW(4);
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EVLDW(5); EVLDW(6); EVLDW(7); EVLDW(8);
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EVLDW(9); EVLDW(10); EVLDW(11); EVLDW(12);
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EVLDW(13); EVLDW(14); EVLDW(15); EVLDW(16);
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EVLDW(17); EVLDW(18); EVLDW(19); EVLDW(20);
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EVLDW(21); EVLDW(22); EVLDW(23); EVLDW(24);
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EVLDW(25); EVLDW(26); EVLDW(27); EVLDW(28);
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EVLDW(29); EVLDW(30); EVLDW(31); EVLDW(0);
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#undef EVLDW
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isync();
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mtmsr(msr);
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}
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void
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save_vec(struct thread *td)
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{
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struct pcb *pcb;
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pcb = td->td_pcb;
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save_vec_int(td);
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/*
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* Clear the current vec thread and pcb's CPU id
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* XXX should this be left clear to allow lazy save/restore ?
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*/
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pcb->pcb_veccpu = INT_MAX;
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PCPU_SET(vecthread, NULL);
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}
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/*
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* Save SPE state without dropping ownership. This will only save state if
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* the current vector-thread is `td'.
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*/
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void
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save_vec_nodrop(struct thread *td)
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{
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struct thread *vtd;
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vtd = PCPU_GET(vecthread);
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if (td != vtd) {
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return;
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}
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save_vec_int(td);
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}
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#define SPE_INST_MASK 0x31f
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#define EADD 0x200
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#define ESUB 0x201
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#define EABS 0x204
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#define ENABS 0x205
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#define ENEG 0x206
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#define EMUL 0x208
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#define EDIV 0x209
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#define ECMPGT 0x20c
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#define ECMPLT 0x20d
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#define ECMPEQ 0x20e
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#define ECFUI 0x210
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#define ECFSI 0x211
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#define ECTUI 0x214
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#define ECTSI 0x215
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#define ECTUF 0x216
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#define ECTSF 0x217
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#define ECTUIZ 0x218
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#define ECTSIZ 0x21a
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#define SPE 0x4
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#define SPFP 0x6
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#define DPFP 0x7
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#define SPE_OPC 4
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#define OPC_SHIFT 26
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#define EVFSADD 0x280
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#define EVFSSUB 0x281
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#define EVFSABS 0x284
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#define EVFSNABS 0x285
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#define EVFSNEG 0x286
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#define EVFSMUL 0x288
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#define EVFSDIV 0x289
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#define EVFSCMPGT 0x28c
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#define EVFSCMPLT 0x28d
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#define EVFSCMPEQ 0x28e
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#define EVFSCFUI 0x290
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#define EVFSCFSI 0x291
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#define EVFSCTUI 0x294
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#define EVFSCTSI 0x295
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#define EVFSCTUF 0x296
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#define EVFSCTSF 0x297
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#define EVFSCTUIZ 0x298
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#define EVFSCTSIZ 0x29a
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#define EFSADD 0x2c0
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#define EFSSUB 0x2c1
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#define EFSABS 0x2c4
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#define EFSNABS 0x2c5
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#define EFSNEG 0x2c6
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#define EFSMUL 0x2c8
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#define EFSDIV 0x2c9
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#define EFSCMPGT 0x2cc
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#define EFSCMPLT 0x2cd
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#define EFSCMPEQ 0x2ce
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#define EFSCFD 0x2cf
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#define EFSCFUI 0x2d0
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#define EFSCFSI 0x2d1
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#define EFSCTUI 0x2d4
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#define EFSCTSI 0x2d5
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#define EFSCTUF 0x2d6
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#define EFSCTSF 0x2d7
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#define EFSCTUIZ 0x2d8
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#define EFSCTSIZ 0x2da
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#define EFDADD 0x2e0
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#define EFDSUB 0x2e1
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#define EFDABS 0x2e4
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#define EFDNABS 0x2e5
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#define EFDNEG 0x2e6
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#define EFDMUL 0x2e8
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#define EFDDIV 0x2e9
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#define EFDCMPGT 0x2ec
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#define EFDCMPLT 0x2ed
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#define EFDCMPEQ 0x2ee
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#define EFDCFS 0x2ef
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#define EFDCFUI 0x2f0
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#define EFDCFSI 0x2f1
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#define EFDCTUI 0x2f4
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#define EFDCTSI 0x2f5
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#define EFDCTUF 0x2f6
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#define EFDCTSF 0x2f7
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#define EFDCTUIZ 0x2f8
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#define EFDCTSIZ 0x2fa
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enum {
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NONE,
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SINGLE,
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DOUBLE,
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VECTOR,
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};
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static uint32_t fpscr_to_spefscr(uint32_t fpscr)
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{
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uint32_t spefscr;
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spefscr = 0;
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if (fpscr & FPSCR_VX)
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spefscr |= SPEFSCR_FINV;
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if (fpscr & FPSCR_OX)
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spefscr |= SPEFSCR_FOVF;
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if (fpscr & FPSCR_UX)
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spefscr |= SPEFSCR_FUNF;
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if (fpscr & FPSCR_ZX)
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spefscr |= SPEFSCR_FDBZ;
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if (fpscr & FPSCR_XX)
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spefscr |= SPEFSCR_FX;
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return (spefscr);
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}
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/* Sign is 0 for unsigned, 1 for signed. */
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static int
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spe_to_int(struct fpemu *fpemu, struct fpn *fpn, uint32_t *val, int sign)
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{
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uint32_t res[2];
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res[0] = fpu_ftox(fpemu, fpn, res);
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if (res[0] != UINT_MAX && res[0] != 0)
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fpemu->fe_cx |= FPSCR_OX;
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else if (sign == 0 && res[0] != 0)
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fpemu->fe_cx |= FPSCR_UX;
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else
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*val = res[1];
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return (0);
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}
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/* Masked instruction */
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/*
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* For compare instructions, returns 1 if success, 0 if not. For all others,
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* returns -1, or -2 if no result needs recorded.
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*/
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static int
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spe_emu_instr(uint32_t instr, struct fpemu *fpemu,
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struct fpn **result, uint32_t *iresult)
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{
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switch (instr & SPE_INST_MASK) {
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case EABS:
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case ENABS:
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case ENEG:
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/* Taken care of elsewhere. */
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break;
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case ECTUIZ:
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fpemu->fe_cx &= ~FPSCR_RN;
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fpemu->fe_cx |= FP_RZ;
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case ECTUI:
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spe_to_int(fpemu, &fpemu->fe_f2, iresult, 0);
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return (-1);
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case ECTSIZ:
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fpemu->fe_cx &= ~FPSCR_RN;
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fpemu->fe_cx |= FP_RZ;
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case ECTSI:
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spe_to_int(fpemu, &fpemu->fe_f2, iresult, 1);
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return (-1);
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case EADD:
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*result = fpu_add(fpemu);
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break;
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case ESUB:
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*result = fpu_sub(fpemu);
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break;
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case EMUL:
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*result = fpu_mul(fpemu);
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break;
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case EDIV:
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*result = fpu_div(fpemu);
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break;
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case ECMPGT:
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fpu_compare(fpemu, 0);
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if (fpemu->fe_cx & FPSCR_FG)
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return (1);
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return (0);
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case ECMPLT:
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fpu_compare(fpemu, 0);
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if (fpemu->fe_cx & FPSCR_FL)
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return (1);
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return (0);
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case ECMPEQ:
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fpu_compare(fpemu, 0);
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if (fpemu->fe_cx & FPSCR_FE)
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return (1);
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return (0);
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default:
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printf("Unknown instruction %x\n", instr);
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}
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return (-1);
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}
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static int
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spe_explode(struct fpemu *fe, struct fpn *fp, uint32_t type,
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uint32_t hi, uint32_t lo)
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{
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uint32_t s;
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fp->fp_sign = hi >> 31;
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fp->fp_sticky = 0;
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switch (type) {
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case SINGLE:
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s = fpu_stof(fp, hi);
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break;
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case DOUBLE:
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s = fpu_dtof(fp, hi, lo);
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break;
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}
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if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) {
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/*
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* Input is a signalling NaN. All operations that return
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* an input NaN operand put it through a ``NaN conversion'',
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* which basically just means ``turn on the quiet bit''.
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* We do this here so that all NaNs internally look quiet
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* (we can tell signalling ones by their class).
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*/
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fp->fp_mant[0] |= FP_QUIETBIT;
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fe->fe_cx = FPSCR_VXSNAN; /* assert invalid operand */
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s = FPC_SNAN;
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}
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fp->fp_class = s;
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return (0);
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}
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/*
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* Save the high word of a 64-bit GPR for manipulation in the exception handler.
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*/
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static uint32_t
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spe_save_reg_high(int reg)
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{
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uint32_t vec[2];
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#define EVSTDW(n) case n: __asm __volatile ("evstdw %1,0(%0)" \
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:: "b"(vec), "n"(n)); break;
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switch (reg) {
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EVSTDW(0); EVSTDW(1); EVSTDW(2); EVSTDW(3);
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EVSTDW(4); EVSTDW(5); EVSTDW(6); EVSTDW(7);
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EVSTDW(8); EVSTDW(9); EVSTDW(10); EVSTDW(11);
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EVSTDW(12); EVSTDW(13); EVSTDW(14); EVSTDW(15);
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EVSTDW(16); EVSTDW(17); EVSTDW(18); EVSTDW(19);
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EVSTDW(20); EVSTDW(21); EVSTDW(22); EVSTDW(23);
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EVSTDW(24); EVSTDW(25); EVSTDW(26); EVSTDW(27);
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EVSTDW(28); EVSTDW(29); EVSTDW(30); EVSTDW(31);
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}
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#undef EVSTDW
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return (vec[0]);
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}
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/*
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* Load the given value into the high word of the requested register.
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*/
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static void
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spe_load_reg_high(int reg, uint32_t val)
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{
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#define EVLDW(n) case n: __asm __volatile("evmergelo "#n",%0,"#n \
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:: "r"(val)); break;
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switch (reg) {
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EVLDW(1); EVLDW(2); EVLDW(3); EVLDW(4);
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EVLDW(5); EVLDW(6); EVLDW(7); EVLDW(8);
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EVLDW(9); EVLDW(10); EVLDW(11); EVLDW(12);
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EVLDW(13); EVLDW(14); EVLDW(15); EVLDW(16);
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EVLDW(17); EVLDW(18); EVLDW(19); EVLDW(20);
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EVLDW(21); EVLDW(22); EVLDW(23); EVLDW(24);
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EVLDW(25); EVLDW(26); EVLDW(27); EVLDW(28);
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EVLDW(29); EVLDW(30); EVLDW(31); EVLDW(0);
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}
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#undef EVLDW
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}
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void
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spe_handle_fpdata(struct trapframe *frame)
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{
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struct fpemu fpemu;
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struct fpn *result;
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uint32_t instr, instr_sec_op;
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uint32_t cr_shift, ra, rb, rd, src;
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uint32_t high, low, res, tmp; /* For vector operations. */
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uint32_t spefscr = 0;
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uint32_t ftod_res[2];
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int width; /* Single, Double, Vector, Integer */
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int err;
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uint32_t msr;
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err = fueword32((void *)frame->srr0, &instr);
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if (err != 0)
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return;
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/* Fault. */;
|
|
|
|
if ((instr >> OPC_SHIFT) != SPE_OPC)
|
|
return;
|
|
|
|
msr = mfmsr();
|
|
/*
|
|
* 'cr' field is the upper 3 bits of rd. Magically, since a) rd is 5
|
|
* bits, b) each 'cr' field is 4 bits, and c) Only the 'GT' bit is
|
|
* modified for most compare operations, the full value of rd can be
|
|
* used as a shift value.
|
|
*/
|
|
rd = (instr >> 21) & 0x1f;
|
|
ra = (instr >> 16) & 0x1f;
|
|
rb = (instr >> 11) & 0x1f;
|
|
src = (instr >> 5) & 0x7;
|
|
cr_shift = 28 - (rd & 0x1f);
|
|
|
|
instr_sec_op = (instr & 0x7ff);
|
|
|
|
memset(&fpemu, 0, sizeof(fpemu));
|
|
|
|
width = NONE;
|
|
switch (src) {
|
|
case SPE:
|
|
mtmsr(msr | PSL_VEC);
|
|
switch (instr_sec_op) {
|
|
case EVFSABS:
|
|
high = spe_save_reg_high(ra) & ~(1U << 31);
|
|
frame->fixreg[rd] = frame->fixreg[ra] & ~(1U << 31);
|
|
spe_load_reg_high(rd, high);
|
|
break;
|
|
case EVFSNABS:
|
|
high = spe_save_reg_high(ra) | (1U << 31);
|
|
frame->fixreg[rd] = frame->fixreg[ra] | (1U << 31);
|
|
spe_load_reg_high(rd, high);
|
|
break;
|
|
case EVFSNEG:
|
|
high = spe_save_reg_high(ra) ^ (1U << 31);
|
|
frame->fixreg[rd] = frame->fixreg[ra] ^ (1U << 31);
|
|
spe_load_reg_high(rd, high);
|
|
break;
|
|
default:
|
|
/* High word */
|
|
spe_explode(&fpemu, &fpemu.fe_f1, SINGLE,
|
|
spe_save_reg_high(ra), 0);
|
|
spe_explode(&fpemu, &fpemu.fe_f2, SINGLE,
|
|
spe_save_reg_high(rb), 0);
|
|
high = spe_emu_instr(instr_sec_op, &fpemu, &result,
|
|
&tmp);
|
|
|
|
if (high < 0)
|
|
spe_load_reg_high(rd, tmp);
|
|
|
|
spefscr = fpscr_to_spefscr(fpemu.fe_cx) << 16;
|
|
/* Clear the fpemu to start over on the lower bits. */
|
|
memset(&fpemu, 0, sizeof(fpemu));
|
|
|
|
/* Now low word */
|
|
spe_explode(&fpemu, &fpemu.fe_f1, SINGLE,
|
|
frame->fixreg[ra], 0);
|
|
spe_explode(&fpemu, &fpemu.fe_f2, SINGLE,
|
|
frame->fixreg[rb], 0);
|
|
spefscr |= fpscr_to_spefscr(fpemu.fe_cx);
|
|
low = spe_emu_instr(instr_sec_op, &fpemu, &result,
|
|
&frame->fixreg[rd]);
|
|
if (instr_sec_op == EVFSCMPEQ ||
|
|
instr_sec_op == EVFSCMPGT ||
|
|
instr_sec_op == EVFSCMPLT) {
|
|
res = (high << 3) | (low << 2) |
|
|
((high | low) << 1) | (high & low);
|
|
width = NONE;
|
|
} else
|
|
width = VECTOR;
|
|
break;
|
|
}
|
|
goto end;
|
|
|
|
case SPFP:
|
|
switch (instr_sec_op) {
|
|
case EFSABS:
|
|
frame->fixreg[rd] = frame->fixreg[ra] & ~(1U << 31);
|
|
break;
|
|
case EFSNABS:
|
|
frame->fixreg[rd] = frame->fixreg[ra] | (1U << 31);
|
|
break;
|
|
case EFSNEG:
|
|
frame->fixreg[rd] = frame->fixreg[ra] ^ (1U << 31);
|
|
break;
|
|
case EFSCFD:
|
|
mtmsr(msr | PSL_VEC);
|
|
spe_explode(&fpemu, &fpemu.fe_f3, DOUBLE,
|
|
spe_save_reg_high(rb), frame->fixreg[rb]);
|
|
result = &fpemu.fe_f3;
|
|
width = SINGLE;
|
|
break;
|
|
default:
|
|
spe_explode(&fpemu, &fpemu.fe_f1, SINGLE,
|
|
frame->fixreg[ra], 0);
|
|
spe_explode(&fpemu, &fpemu.fe_f2, SINGLE,
|
|
frame->fixreg[rb], 0);
|
|
width = SINGLE;
|
|
}
|
|
break;
|
|
case DPFP:
|
|
mtmsr(msr | PSL_VEC);
|
|
switch (instr_sec_op) {
|
|
case EFDABS:
|
|
high = spe_save_reg_high(ra) & ~(1U << 31);
|
|
frame->fixreg[rd] = frame->fixreg[ra];
|
|
spe_load_reg_high(rd, high);
|
|
break;
|
|
case EFDNABS:
|
|
high = spe_save_reg_high(ra) | (1U << 31);
|
|
frame->fixreg[rd] = frame->fixreg[ra];
|
|
spe_load_reg_high(rd, high);
|
|
break;
|
|
case EFDNEG:
|
|
high = spe_save_reg_high(ra) ^ (1U << 31);
|
|
frame->fixreg[rd] = frame->fixreg[ra];
|
|
spe_load_reg_high(rd, high);
|
|
break;
|
|
case EFDCFS:
|
|
spe_explode(&fpemu, &fpemu.fe_f3, SINGLE,
|
|
frame->fixreg[rb], 0);
|
|
result = &fpemu.fe_f3;
|
|
width = DOUBLE;
|
|
break;
|
|
default:
|
|
spe_explode(&fpemu, &fpemu.fe_f1, DOUBLE,
|
|
spe_save_reg_high(ra), frame->fixreg[ra]);
|
|
spe_explode(&fpemu, &fpemu.fe_f2, DOUBLE,
|
|
spe_save_reg_high(rb), frame->fixreg[rb]);
|
|
width = DOUBLE;
|
|
}
|
|
break;
|
|
}
|
|
switch (instr_sec_op) {
|
|
case EFDCFS:
|
|
case EFSCFD:
|
|
/* Already handled. */
|
|
break;
|
|
default:
|
|
res = spe_emu_instr(instr_sec_op, &fpemu, &result,
|
|
&frame->fixreg[rd]);
|
|
if (res != -1)
|
|
res <<= 2;
|
|
break;
|
|
}
|
|
|
|
switch (instr_sec_op & SPE_INST_MASK) {
|
|
case ECMPEQ:
|
|
case ECMPGT:
|
|
case ECMPLT:
|
|
frame->cr &= ~(0xf << cr_shift);
|
|
frame->cr |= (res << cr_shift);
|
|
break;
|
|
case ECTUI:
|
|
case ECTUIZ:
|
|
case ECTSI:
|
|
case ECTSIZ:
|
|
break;
|
|
default:
|
|
switch (width) {
|
|
case NONE:
|
|
case VECTOR:
|
|
break;
|
|
case SINGLE:
|
|
frame->fixreg[rd] = fpu_ftos(&fpemu, result);
|
|
break;
|
|
case DOUBLE:
|
|
spe_load_reg_high(rd, fpu_ftod(&fpemu, result, ftod_res));
|
|
frame->fixreg[rd] = ftod_res[1];
|
|
break;
|
|
default:
|
|
panic("Unknown storage width %d", width);
|
|
break;
|
|
}
|
|
}
|
|
|
|
end:
|
|
spefscr |= (mfspr(SPR_SPEFSCR) & ~SPEFSCR_FINVS);
|
|
mtspr(SPR_SPEFSCR, spefscr);
|
|
frame->srr0 += 4;
|
|
mtmsr(msr);
|
|
|
|
return;
|
|
}
|
|
|
|
void
|
|
spe_handle_fpround(struct trapframe *frame)
|
|
{
|
|
|
|
/*
|
|
* Punt fpround exceptions for now. This leaves the truncated result in
|
|
* the register. We'll deal with overflow/underflow later.
|
|
*/
|
|
return;
|
|
}
|