7de649170f
Every other architecture defines this and this is required for interrupts to work when using QEMU's PCI VirtIO devices (which all report an interrupt line of 0) for two reasons. Firstly, interrupt line 0 is wrong; they use one of 0x20-0x23 with the lines being cycled across devices like normal. Moreover, RISC-V uses INTRNG, whose IRQs are virtual as indices into its irq_map, so even if we have the right interrupt line we still need to try and route the interrupt in order to ultimately call into intr_map_irq and get back a unique index into the map for the given line, otherwise we will use whatever happens to be in irq_map[line] (which for QEMU where the line is initialised to 0 results in using the first allocated interrupt, namely the RTC on IRQ 11 at time of commit). Note that pci_assign_interrupt will still do the wrong thing for INTRNG when using a tunable, as it will bypass INTRNG entirely and use the tunable's value as the index into irq_map, when it should instead (indirectly) call intr_map_irq to allocate a new entry for the given IRQ and treat the tunable as stating the physical line in use, which is what one would expect. This, however, is a problem shared by all INTRNG architectures, and not exclusive to RISC-V. Reviewed by: kib Approved by: kib Differential Revision: https://reviews.freebsd.org/D26564
120 lines
3.6 KiB
C
120 lines
3.6 KiB
C
/*-
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)param.h 5.8 (Berkeley) 6/28/91
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PARAM_H_
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#define _MACHINE_PARAM_H_
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/*
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* Machine dependent constants for RISC-V.
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*/
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#include <machine/_align.h>
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#define STACKALIGNBYTES (16 - 1)
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#define STACKALIGN(p) ((uint64_t)(p) & ~STACKALIGNBYTES)
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#define __PCI_REROUTE_INTERRUPT
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#ifndef MACHINE
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#define MACHINE "riscv"
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#endif
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#ifndef MACHINE_ARCH
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/* Always use the hard-float arch for the kernel. */
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#if !defined(_KERNEL) && defined(__riscv_float_abi_soft)
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#define MACHINE_ARCH "riscv64sf"
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#else
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#define MACHINE_ARCH "riscv64"
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#endif
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#endif
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#ifdef _KERNEL
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#define MACHINE_ARCHES "riscv64 riscv64sf"
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#endif
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#ifdef SMP
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#ifndef MAXCPU
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#define MAXCPU 16
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#endif
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#else
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#define MAXCPU 1
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#endif
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#ifndef MAXMEMDOM
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#define MAXMEMDOM 1
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#endif
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#define ALIGNBYTES _ALIGNBYTES
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#define ALIGN(p) _ALIGN(p)
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/*
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* ALIGNED_POINTER is a boolean macro that checks whether an address
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* is valid to fetch data elements of type t from on this architecture.
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* This does not reflect the optimal alignment, just the possibility
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* (within reasonable limits).
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*/
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#define ALIGNED_POINTER(p, t) ((((u_long)(p)) & (sizeof(t) - 1)) == 0)
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/*
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* CACHE_LINE_SIZE is the compile-time maximum cache line size for an
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* architecture. It should be used with appropriate caution.
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*/
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#define CACHE_LINE_SHIFT 6
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#define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT)
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#define PAGE_SHIFT 12
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#define PAGE_SIZE (1 << PAGE_SHIFT) /* Page size */
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#define PAGE_MASK (PAGE_SIZE - 1)
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#define MAXPAGESIZES 3 /* maximum number of supported page sizes */
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#ifndef KSTACK_PAGES
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#define KSTACK_PAGES 4 /* pages of kernel stack (with pcb) */
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#endif
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#define KSTACK_GUARD_PAGES 1 /* pages of kstack guard; 0 disables */
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#define PCPU_PAGES 1
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/*
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* Mach derived conversion macros
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*/
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#define round_page(x) (((unsigned long)(x) + PAGE_MASK) & ~PAGE_MASK)
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#define trunc_page(x) ((unsigned long)(x) & ~PAGE_MASK)
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#define atop(x) ((unsigned long)(x) >> PAGE_SHIFT)
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#define ptoa(x) ((unsigned long)(x) << PAGE_SHIFT)
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#define riscv_btop(x) ((unsigned long)(x) >> PAGE_SHIFT)
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#define riscv_ptob(x) ((unsigned long)(x) << PAGE_SHIFT)
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#define pgtok(x) ((unsigned long)(x) * (PAGE_SIZE / 1024))
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#endif /* !_MACHINE_PARAM_H_ */
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