85fc5c3b93
so that it isn't exposured unless needed. In particular this means that it's easier to tune the memory layout based on board details. While here, remove inclusion of <machine/intr.h> from mvreg.h. This also contains exposure to SoC specifics in MI drivers, because NIRQ depends on the SoC.
1469 lines
32 KiB
C
1469 lines
32 KiB
C
/*-
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* Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
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* All rights reserved.
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*
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* Developed by Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of MARVELL nor the names of contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <arm/mv/mvreg.h>
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#include <arm/mv/mvvar.h>
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#include <arm/mv/mvwin.h>
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static int win_eth_can_remap(int i);
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static int decode_win_cpu_valid(void);
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static int decode_win_usb_valid(void);
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static int decode_win_eth_valid(void);
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static int decode_win_pcie_valid(void);
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static int decode_win_sata_valid(void);
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static int decode_win_cesa_valid(void);
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static void decode_win_cpu_setup(void);
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static void decode_win_usb_setup(void);
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static void decode_win_eth_setup(uint32_t base);
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static void decode_win_pcie_setup(uint32_t base);
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static void decode_win_sata_setup(void);
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static void decode_win_cesa_setup(void);
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static void decode_win_cesa_dump(void);
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static void decode_win_usb_dump(void);
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static uint32_t used_cpu_wins;
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uint32_t
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read_cpu_ctrl(uint32_t reg)
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{
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return (bus_space_read_4(obio_tag, MV_CPU_CONTROL_BASE, reg));
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}
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void
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write_cpu_ctrl(uint32_t reg, uint32_t val)
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{
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bus_space_write_4(obio_tag, MV_CPU_CONTROL_BASE, reg, val);
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}
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void
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cpu_reset(void)
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{
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write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN);
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write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
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while (1);
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}
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uint32_t
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cpu_extra_feat(void)
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{
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uint32_t dev, rev;
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uint32_t ef = 0;
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soc_id(&dev, &rev);
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if (dev == MV_DEV_88F6281 || dev == MV_DEV_MV78100_Z0 ||
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dev == MV_DEV_MV78100)
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__asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef));
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else if (dev == MV_DEV_88F5182 || dev == MV_DEV_88F5281)
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__asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef));
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else if (bootverbose)
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printf("This ARM Core does not support any extra features\n");
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return (ef);
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}
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uint32_t
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soc_power_ctrl_get(uint32_t mask)
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{
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if (mask != CPU_PM_CTRL_NONE)
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mask &= read_cpu_ctrl(CPU_PM_CTRL);
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return (mask);
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}
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void
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soc_id(uint32_t *dev, uint32_t *rev)
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{
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/*
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* Notice: system identifiers are available in the registers range of
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* PCIE controller, so using this function is only allowed (and
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* possible) after the internal registers range has been mapped in via
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* pmap_devmap_bootstrap().
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*/
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*dev = bus_space_read_4(obio_tag, MV_PCIE_BASE, 0) >> 16;
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*rev = bus_space_read_4(obio_tag, MV_PCIE_BASE, 8) & 0xff;
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}
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void
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soc_identify(void)
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{
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uint32_t d, r;
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const char *dev;
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const char *rev;
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soc_id(&d, &r);
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printf("SOC: ");
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if (bootverbose)
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printf("(0x%4x:0x%02x) ", d, r);
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rev = "";
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switch (d) {
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case MV_DEV_88F5181:
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dev = "Marvell 88F5181";
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if (r == 3)
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rev = "B1";
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break;
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case MV_DEV_88F5182:
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dev = "Marvell 88F5182";
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if (r == 2)
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rev = "A2";
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break;
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case MV_DEV_88F5281:
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dev = "Marvell 88F5281";
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if (r == 4)
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rev = "D0";
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else if (r == 5)
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rev = "D1";
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else if (r == 6)
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rev = "D2";
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break;
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case MV_DEV_88F6281:
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dev = "Marvell 88F6281";
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if (r == 0)
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rev = "Z0";
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else if (r == 2)
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rev = "A0";
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break;
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case MV_DEV_MV78100_Z0:
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dev = "Marvell MV78100 Z0";
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break;
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case MV_DEV_MV78100:
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dev = "Marvell MV78100";
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break;
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default:
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dev = "UNKNOWN";
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break;
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}
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printf("%s", dev);
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if (*rev != '\0')
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printf(" rev %s", rev);
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printf(", TClock %dMHz\n", get_tclk() / 1000 / 1000);
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/* TODO add info on currently set endianess */
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}
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int
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soc_decode_win(void)
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{
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uint32_t dev, rev;
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/* Retrieve our ID: some windows facilities vary between SoC models */
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soc_id(&dev, &rev);
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if (decode_win_cpu_valid() != 1 || decode_win_usb_valid() != 1 ||
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decode_win_eth_valid() != 1 || decode_win_idma_valid() != 1 ||
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decode_win_pcie_valid() != 1 || decode_win_sata_valid() != 1 ||
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decode_win_cesa_valid() != 1)
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return(-1);
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decode_win_cpu_setup();
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decode_win_usb_setup();
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decode_win_eth_setup(MV_ETH0_BASE);
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if (dev == MV_DEV_MV78100 || dev == MV_DEV_MV78100_Z0)
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decode_win_eth_setup(MV_ETH1_BASE);
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if (dev == MV_DEV_88F6281 || dev == MV_DEV_MV78100 ||
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dev == MV_DEV_MV78100_Z0)
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decode_win_cesa_setup();
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decode_win_idma_setup();
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decode_win_xor_setup();
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if (dev == MV_DEV_MV78100 || dev == MV_DEV_MV78100_Z0) {
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decode_win_pcie_setup(MV_PCIE00_BASE);
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decode_win_pcie_setup(MV_PCIE01_BASE);
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decode_win_pcie_setup(MV_PCIE02_BASE);
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decode_win_pcie_setup(MV_PCIE03_BASE);
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decode_win_pcie_setup(MV_PCIE10_BASE);
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decode_win_pcie_setup(MV_PCIE11_BASE);
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decode_win_pcie_setup(MV_PCIE12_BASE);
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decode_win_pcie_setup(MV_PCIE13_BASE);
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} else
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decode_win_pcie_setup(MV_PCIE_BASE);
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if (dev != MV_DEV_88F5281)
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decode_win_sata_setup();
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return (0);
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}
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/**************************************************************************
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* Decode windows registers accessors
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**************************************************************************/
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WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
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WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
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WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
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WIN_REG_IDX_RD(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
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WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
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WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
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WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
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WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
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WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)
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WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)
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WIN_REG_IDX_RD2(win_usb, cr, MV_WIN_USB_CTRL, MV_USB_AWR_BASE)
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WIN_REG_IDX_RD2(win_usb, br, MV_WIN_USB_BASE, MV_USB_AWR_BASE)
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WIN_REG_IDX_WR2(win_usb, cr, MV_WIN_USB_CTRL, MV_USB_AWR_BASE)
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WIN_REG_IDX_WR2(win_usb, br, MV_WIN_USB_BASE, MV_USB_AWR_BASE)
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WIN_REG_IDX_RD(win_cesa, cr, MV_WIN_CESA_CTRL, MV_CESA_BASE)
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WIN_REG_IDX_RD(win_cesa, br, MV_WIN_CESA_BASE, MV_CESA_BASE)
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WIN_REG_IDX_WR(win_cesa, cr, MV_WIN_CESA_CTRL, MV_CESA_BASE)
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WIN_REG_IDX_WR(win_cesa, br, MV_WIN_CESA_BASE, MV_CESA_BASE)
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WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE)
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WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE)
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WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP)
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WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE)
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WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE)
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WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP)
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WIN_REG_IDX_RD2(win_xor, br, MV_WIN_XOR_BASE, MV_XOR_BASE)
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WIN_REG_IDX_RD2(win_xor, sz, MV_WIN_XOR_SIZE, MV_XOR_BASE)
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WIN_REG_IDX_RD2(win_xor, har, MV_WIN_XOR_REMAP, MV_XOR_BASE)
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WIN_REG_IDX_RD2(win_xor, ctrl, MV_WIN_XOR_CTRL, MV_XOR_BASE)
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WIN_REG_IDX_WR2(win_xor, br, MV_WIN_XOR_BASE, MV_XOR_BASE)
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WIN_REG_IDX_WR2(win_xor, sz, MV_WIN_XOR_SIZE, MV_XOR_BASE)
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WIN_REG_IDX_WR2(win_xor, har, MV_WIN_XOR_REMAP, MV_XOR_BASE)
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WIN_REG_IDX_WR2(win_xor, ctrl, MV_WIN_XOR_CTRL, MV_XOR_BASE)
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WIN_REG_BASE_RD(win_eth, bare, 0x290)
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WIN_REG_BASE_RD(win_eth, epap, 0x294)
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WIN_REG_BASE_WR(win_eth, bare, 0x290)
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WIN_REG_BASE_WR(win_eth, epap, 0x294)
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WIN_REG_BASE_IDX_RD(win_pcie, cr, MV_WIN_PCIE_CTRL);
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WIN_REG_BASE_IDX_RD(win_pcie, br, MV_WIN_PCIE_BASE);
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WIN_REG_BASE_IDX_RD(win_pcie, remap, MV_WIN_PCIE_REMAP);
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WIN_REG_BASE_IDX_WR(win_pcie, cr, MV_WIN_PCIE_CTRL);
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WIN_REG_BASE_IDX_WR(win_pcie, br, MV_WIN_PCIE_BASE);
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WIN_REG_BASE_IDX_WR(win_pcie, remap, MV_WIN_PCIE_REMAP);
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WIN_REG_BASE_IDX_WR(pcie, bar, MV_PCIE_BAR);
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WIN_REG_IDX_RD(win_idma, br, MV_WIN_IDMA_BASE, MV_IDMA_BASE)
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WIN_REG_IDX_RD(win_idma, sz, MV_WIN_IDMA_SIZE, MV_IDMA_BASE)
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WIN_REG_IDX_RD(win_idma, har, MV_WIN_IDMA_REMAP, MV_IDMA_BASE)
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WIN_REG_IDX_RD(win_idma, cap, MV_WIN_IDMA_CAP, MV_IDMA_BASE)
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WIN_REG_IDX_WR(win_idma, br, MV_WIN_IDMA_BASE, MV_IDMA_BASE)
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WIN_REG_IDX_WR(win_idma, sz, MV_WIN_IDMA_SIZE, MV_IDMA_BASE)
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WIN_REG_IDX_WR(win_idma, har, MV_WIN_IDMA_REMAP, MV_IDMA_BASE)
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WIN_REG_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP, MV_IDMA_BASE)
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WIN_REG_RD(win_idma, bare, 0xa80, MV_IDMA_BASE)
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WIN_REG_WR(win_idma, bare, 0xa80, MV_IDMA_BASE)
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WIN_REG_IDX_RD(win_sata, cr, MV_WIN_SATA_CTRL, MV_SATAHC_BASE);
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WIN_REG_IDX_RD(win_sata, br, MV_WIN_SATA_BASE, MV_SATAHC_BASE);
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WIN_REG_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL, MV_SATAHC_BASE);
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WIN_REG_IDX_WR(win_sata, br, MV_WIN_SATA_BASE, MV_SATAHC_BASE);
|
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|
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/**************************************************************************
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* Decode windows helper routines
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**************************************************************************/
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void
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soc_dump_decode_win(void)
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{
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uint32_t dev, rev;
|
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int i;
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|
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soc_id(&dev, &rev);
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|
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for (i = 0; i < MV_WIN_CPU_MAX; i++) {
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printf("CPU window#%d: c 0x%08x, b 0x%08x", i,
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win_cpu_cr_read(i),
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win_cpu_br_read(i));
|
|
|
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if (win_cpu_can_remap(i))
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printf(", rl 0x%08x, rh 0x%08x",
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win_cpu_remap_l_read(i),
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win_cpu_remap_h_read(i));
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|
|
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printf("\n");
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}
|
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printf("Internal regs base: 0x%08x\n",
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bus_space_read_4(obio_tag, MV_INTREGS_BASE, 0));
|
|
|
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for (i = 0; i < MV_WIN_DDR_MAX; i++)
|
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printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i,
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ddr_br_read(i), ddr_sz_read(i));
|
|
|
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for (i = 0; i < MV_WIN_ETH_MAX; i++) {
|
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printf("ETH window#%d: b 0x%08x, s 0x%08x", i,
|
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win_eth_br_read(MV_ETH0_BASE, i),
|
|
win_eth_sz_read(MV_ETH0_BASE, i));
|
|
|
|
if (win_eth_can_remap(i))
|
|
printf(", ha 0x%08x",
|
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win_eth_har_read(MV_ETH0_BASE, i));
|
|
|
|
printf("\n");
|
|
}
|
|
printf("ETH windows: bare 0x%08x, epap 0x%08x\n",
|
|
win_eth_bare_read(MV_ETH0_BASE),
|
|
win_eth_epap_read(MV_ETH0_BASE));
|
|
|
|
decode_win_idma_dump();
|
|
decode_win_cesa_dump();
|
|
decode_win_usb_dump();
|
|
printf("\n");
|
|
}
|
|
|
|
/**************************************************************************
|
|
* CPU windows routines
|
|
**************************************************************************/
|
|
int
|
|
win_cpu_can_remap(int i)
|
|
{
|
|
uint32_t dev, rev;
|
|
|
|
soc_id(&dev, &rev);
|
|
|
|
/* Depending on the SoC certain windows have remap capability */
|
|
if ((dev == MV_DEV_88F5182 && i < 2) ||
|
|
(dev == MV_DEV_88F5281 && i < 4) ||
|
|
(dev == MV_DEV_88F6281 && i < 4) ||
|
|
(dev == MV_DEV_MV78100 && i < 8) ||
|
|
(dev == MV_DEV_MV78100_Z0 && i < 8))
|
|
return (1);
|
|
|
|
return (0);
|
|
}
|
|
|
|
/* XXX This should check for overlapping remap fields too.. */
|
|
int
|
|
decode_win_overlap(int win, int win_no, const struct decode_win *wintab)
|
|
{
|
|
const struct decode_win *tab;
|
|
int i;
|
|
|
|
tab = wintab;
|
|
|
|
for (i = 0; i < win_no; i++, tab++) {
|
|
if (i == win)
|
|
/* Skip self */
|
|
continue;
|
|
|
|
if ((tab->base + tab->size - 1) < (wintab + win)->base)
|
|
continue;
|
|
|
|
else if (((wintab + win)->base + (wintab + win)->size - 1) <
|
|
tab->base)
|
|
continue;
|
|
else
|
|
return (i);
|
|
}
|
|
|
|
return (-1);
|
|
}
|
|
|
|
static int
|
|
decode_win_cpu_valid(void)
|
|
{
|
|
int i, j, rv;
|
|
uint32_t b, e, s;
|
|
|
|
if (cpu_wins_no > MV_WIN_CPU_MAX) {
|
|
printf("CPU windows: too many entries: %d\n", cpu_wins_no);
|
|
return (-1);
|
|
}
|
|
|
|
rv = 1;
|
|
for (i = 0; i < cpu_wins_no; i++) {
|
|
|
|
if (cpu_wins[i].target == 0) {
|
|
printf("CPU window#%d: DDR target window is not "
|
|
"supposed to be reprogrammed!\n", i);
|
|
rv = 0;
|
|
}
|
|
|
|
if (cpu_wins[i].remap >= 0 && win_cpu_can_remap(i) != 1) {
|
|
printf("CPU window#%d: not capable of remapping, but "
|
|
"val 0x%08x defined\n", i, cpu_wins[i].remap);
|
|
rv = 0;
|
|
}
|
|
|
|
s = cpu_wins[i].size;
|
|
b = cpu_wins[i].base;
|
|
e = b + s - 1;
|
|
if (s > (0xFFFFFFFF - b + 1)) {
|
|
/*
|
|
* XXX this boundary check should account for 64bit
|
|
* and remapping..
|
|
*/
|
|
printf("CPU window#%d: no space for size 0x%08x at "
|
|
"0x%08x\n", i, s, b);
|
|
rv = 0;
|
|
continue;
|
|
}
|
|
|
|
j = decode_win_overlap(i, cpu_wins_no, &cpu_wins[0]);
|
|
if (j >= 0) {
|
|
printf("CPU window#%d: (0x%08x - 0x%08x) overlaps "
|
|
"with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
|
|
cpu_wins[j].base,
|
|
cpu_wins[j].base + cpu_wins[j].size - 1);
|
|
rv = 0;
|
|
}
|
|
}
|
|
|
|
return (rv);
|
|
}
|
|
|
|
int
|
|
decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size,
|
|
int remap)
|
|
{
|
|
uint32_t br, cr;
|
|
int win;
|
|
|
|
if (used_cpu_wins >= MV_WIN_CPU_MAX)
|
|
return (-1);
|
|
|
|
win = used_cpu_wins++;
|
|
|
|
br = base & 0xffff0000;
|
|
win_cpu_br_write(win, br);
|
|
|
|
if (win_cpu_can_remap(win)) {
|
|
if (remap >= 0) {
|
|
win_cpu_remap_l_write(win, remap & 0xffff0000);
|
|
win_cpu_remap_h_write(win, 0);
|
|
} else {
|
|
/*
|
|
* Remap function is not used for a given window
|
|
* (capable of remapping) - set remap field with the
|
|
* same value as base.
|
|
*/
|
|
win_cpu_remap_l_write(win, base & 0xffff0000);
|
|
win_cpu_remap_h_write(win, 0);
|
|
}
|
|
}
|
|
|
|
cr = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
|
|
win_cpu_cr_write(win, cr);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
decode_win_cpu_setup(void)
|
|
{
|
|
int i;
|
|
|
|
used_cpu_wins = 0;
|
|
|
|
/* Disable all CPU windows */
|
|
for (i = 0; i < MV_WIN_CPU_MAX; i++) {
|
|
win_cpu_cr_write(i, 0);
|
|
win_cpu_br_write(i, 0);
|
|
if (win_cpu_can_remap(i)) {
|
|
win_cpu_remap_l_write(i, 0);
|
|
win_cpu_remap_h_write(i, 0);
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < cpu_wins_no; i++)
|
|
if (cpu_wins[i].target > 0)
|
|
decode_win_cpu_set(cpu_wins[i].target,
|
|
cpu_wins[i].attr, cpu_wins[i].base,
|
|
cpu_wins[i].size, cpu_wins[i].remap);
|
|
|
|
}
|
|
|
|
/*
|
|
* Check if we're able to cover all active DDR banks.
|
|
*/
|
|
static int
|
|
decode_win_can_cover_ddr(int max)
|
|
{
|
|
int i, c;
|
|
|
|
c = 0;
|
|
for (i = 0; i < MV_WIN_DDR_MAX; i++)
|
|
if (ddr_is_active(i))
|
|
c++;
|
|
|
|
if (c > max) {
|
|
printf("Unable to cover all active DDR banks: "
|
|
"%d, available windows: %d\n", c, max);
|
|
return (0);
|
|
}
|
|
|
|
return (1);
|
|
}
|
|
|
|
/**************************************************************************
|
|
* DDR windows routines
|
|
**************************************************************************/
|
|
int
|
|
ddr_is_active(int i)
|
|
{
|
|
|
|
if (ddr_sz_read(i) & 0x1)
|
|
return (1);
|
|
|
|
return (0);
|
|
}
|
|
|
|
uint32_t
|
|
ddr_base(int i)
|
|
{
|
|
|
|
return (ddr_br_read(i) & 0xff000000);
|
|
}
|
|
|
|
uint32_t
|
|
ddr_size(int i)
|
|
{
|
|
|
|
return ((ddr_sz_read(i) | 0x00ffffff) + 1);
|
|
}
|
|
|
|
uint32_t
|
|
ddr_attr(int i)
|
|
{
|
|
|
|
return (i == 0 ? 0xe :
|
|
(i == 1 ? 0xd :
|
|
(i == 2 ? 0xb :
|
|
(i == 3 ? 0x7 : 0xff))));
|
|
}
|
|
|
|
uint32_t
|
|
ddr_target(int i)
|
|
{
|
|
|
|
/* Mbus unit ID is 0x0 for DDR SDRAM controller */
|
|
return (0);
|
|
}
|
|
|
|
/**************************************************************************
|
|
* USB windows routines
|
|
**************************************************************************/
|
|
static int
|
|
decode_win_usb_valid(void)
|
|
{
|
|
|
|
return (decode_win_can_cover_ddr(MV_WIN_USB_MAX));
|
|
}
|
|
|
|
static __inline int
|
|
usb_max_ports(void)
|
|
{
|
|
uint32_t dev, rev;
|
|
|
|
soc_id(&dev, &rev);
|
|
return ((dev == MV_DEV_MV78100 || dev == MV_DEV_MV78100_Z0) ? 3 : 1);
|
|
}
|
|
|
|
static void
|
|
decode_win_usb_dump(void)
|
|
{
|
|
int i, p, m;
|
|
|
|
m = usb_max_ports();
|
|
for (p = 0; p < m; p++)
|
|
for (i = 0; i < MV_WIN_USB_MAX; i++)
|
|
printf("USB window#%d: c 0x%08x, b 0x%08x\n", i,
|
|
win_usb_cr_read(i, p), win_usb_br_read(i, p));
|
|
}
|
|
|
|
/*
|
|
* Set USB decode windows.
|
|
*/
|
|
static void
|
|
decode_win_usb_setup(void)
|
|
{
|
|
uint32_t br, cr;
|
|
int i, j, p, m;
|
|
|
|
/* Disable and clear all USB windows for all ports */
|
|
m = usb_max_ports();
|
|
for (p = 0; p < m; p++) {
|
|
|
|
for (i = 0; i < MV_WIN_USB_MAX; i++) {
|
|
win_usb_cr_write(i, p, 0);
|
|
win_usb_br_write(i, p, 0);
|
|
}
|
|
|
|
/* Only access to active DRAM banks is required */
|
|
for (i = 0; i < MV_WIN_DDR_MAX; i++) {
|
|
if (ddr_is_active(i)) {
|
|
br = ddr_base(i);
|
|
/*
|
|
* XXX for 6281 we should handle Mbus write
|
|
* burst limit field in the ctrl reg
|
|
*/
|
|
cr = (((ddr_size(i) - 1) & 0xffff0000) |
|
|
(ddr_attr(i) << 8) |
|
|
(ddr_target(i) << 4) | 1);
|
|
|
|
/* Set the first free USB window */
|
|
for (j = 0; j < MV_WIN_USB_MAX; j++) {
|
|
if (win_usb_cr_read(j, p) & 0x1)
|
|
continue;
|
|
|
|
win_usb_br_write(j, p, br);
|
|
win_usb_cr_write(j, p, cr);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/**************************************************************************
|
|
* ETH windows routines
|
|
**************************************************************************/
|
|
|
|
static int
|
|
win_eth_can_remap(int i)
|
|
{
|
|
|
|
/* ETH encode windows 0-3 have remap capability */
|
|
if (i < 4)
|
|
return (1);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
eth_bare_read(uint32_t base, int i)
|
|
{
|
|
uint32_t v;
|
|
|
|
v = win_eth_bare_read(base);
|
|
v &= (1 << i);
|
|
|
|
return (v >> i);
|
|
}
|
|
|
|
static void
|
|
eth_bare_write(uint32_t base, int i, int val)
|
|
{
|
|
uint32_t v;
|
|
|
|
v = win_eth_bare_read(base);
|
|
v &= ~(1 << i);
|
|
v |= (val << i);
|
|
win_eth_bare_write(base, v);
|
|
}
|
|
|
|
static void
|
|
eth_epap_write(uint32_t base, int i, int val)
|
|
{
|
|
uint32_t v;
|
|
|
|
v = win_eth_epap_read(base);
|
|
v &= ~(0x3 << (i * 2));
|
|
v |= (val << (i * 2));
|
|
win_eth_epap_write(base, v);
|
|
}
|
|
|
|
static void
|
|
decode_win_eth_setup(uint32_t base)
|
|
{
|
|
uint32_t br, sz;
|
|
int i, j;
|
|
|
|
/* Disable, clear and revoke protection for all ETH windows */
|
|
for (i = 0; i < MV_WIN_ETH_MAX; i++) {
|
|
|
|
eth_bare_write(base, i, 1);
|
|
eth_epap_write(base, i, 0);
|
|
win_eth_br_write(base, i, 0);
|
|
win_eth_sz_write(base, i, 0);
|
|
if (win_eth_can_remap(i))
|
|
win_eth_har_write(base, i, 0);
|
|
}
|
|
|
|
/* Only access to active DRAM banks is required */
|
|
for (i = 0; i < MV_WIN_DDR_MAX; i++)
|
|
if (ddr_is_active(i)) {
|
|
|
|
br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i);
|
|
sz = ((ddr_size(i) - 1) & 0xffff0000);
|
|
|
|
/* Set the first free ETH window */
|
|
for (j = 0; j < MV_WIN_ETH_MAX; j++) {
|
|
if (eth_bare_read(base, j) == 0)
|
|
continue;
|
|
|
|
win_eth_br_write(base, j, br);
|
|
win_eth_sz_write(base, j, sz);
|
|
|
|
/* XXX remapping ETH windows not supported */
|
|
|
|
/* Set protection RW */
|
|
eth_epap_write(base, j, 0x3);
|
|
|
|
/* Enable window */
|
|
eth_bare_write(base, j, 0);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
static int
|
|
decode_win_eth_valid(void)
|
|
{
|
|
|
|
return (decode_win_can_cover_ddr(MV_WIN_ETH_MAX));
|
|
}
|
|
|
|
/**************************************************************************
|
|
* PCIE windows routines
|
|
**************************************************************************/
|
|
|
|
static void
|
|
decode_win_pcie_setup(uint32_t base)
|
|
{
|
|
uint32_t size = 0;
|
|
uint32_t cr, br;
|
|
int i, j;
|
|
|
|
for (i = 0; i < MV_PCIE_BAR_MAX; i++)
|
|
pcie_bar_write(base, i, 0);
|
|
|
|
for (i = 0; i < MV_WIN_PCIE_MAX; i++) {
|
|
win_pcie_cr_write(base, i, 0);
|
|
win_pcie_br_write(base, i, 0);
|
|
win_pcie_remap_write(base, i, 0);
|
|
}
|
|
|
|
for (i = 0; i < MV_WIN_DDR_MAX; i++) {
|
|
if (ddr_is_active(i)) {
|
|
/* Map DDR to BAR 1 */
|
|
cr = (ddr_size(i) - 1) & 0xffff0000;
|
|
size += ddr_size(i) & 0xffff0000;
|
|
cr |= (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1;
|
|
br = ddr_base(i);
|
|
|
|
/* Use the first available PCIE window */
|
|
for (j = 0; j < MV_WIN_PCIE_MAX; j++) {
|
|
if (win_pcie_cr_read(base, j) != 0)
|
|
continue;
|
|
|
|
win_pcie_br_write(base, j, br);
|
|
win_pcie_cr_write(base, j, cr);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Upper 16 bits in BAR register is interpreted as BAR size
|
|
* (in 64 kB units) plus 64kB, so substract 0x10000
|
|
* form value passed to register to get correct value.
|
|
*/
|
|
size -= 0x10000;
|
|
pcie_bar_write(base, 0, size | 1);
|
|
}
|
|
|
|
static int
|
|
decode_win_pcie_valid(void)
|
|
{
|
|
|
|
return (decode_win_can_cover_ddr(MV_WIN_PCIE_MAX));
|
|
}
|
|
|
|
/**************************************************************************
|
|
* IDMA windows routines
|
|
**************************************************************************/
|
|
#if defined(SOC_MV_ORION) || defined(SOC_MV_DISCOVERY)
|
|
static int
|
|
idma_bare_read(int i)
|
|
{
|
|
uint32_t v;
|
|
|
|
v = win_idma_bare_read();
|
|
v &= (1 << i);
|
|
|
|
return (v >> i);
|
|
}
|
|
|
|
static void
|
|
idma_bare_write(int i, int val)
|
|
{
|
|
uint32_t v;
|
|
|
|
v = win_idma_bare_read();
|
|
v &= ~(1 << i);
|
|
v |= (val << i);
|
|
win_idma_bare_write(v);
|
|
}
|
|
|
|
/*
|
|
* Sets channel protection 'val' for window 'w' on channel 'c'
|
|
*/
|
|
static void
|
|
idma_cap_write(int c, int w, int val)
|
|
{
|
|
uint32_t v;
|
|
|
|
v = win_idma_cap_read(c);
|
|
v &= ~(0x3 << (w * 2));
|
|
v |= (val << (w * 2));
|
|
win_idma_cap_write(c, v);
|
|
}
|
|
|
|
/*
|
|
* Set protection 'val' on all channels for window 'w'
|
|
*/
|
|
static void
|
|
idma_set_prot(int w, int val)
|
|
{
|
|
int c;
|
|
|
|
for (c = 0; c < MV_IDMA_CHAN_MAX; c++)
|
|
idma_cap_write(c, w, val);
|
|
}
|
|
|
|
static int
|
|
win_idma_can_remap(int i)
|
|
{
|
|
|
|
/* IDMA decode windows 0-3 have remap capability */
|
|
if (i < 4)
|
|
return (1);
|
|
|
|
return (0);
|
|
}
|
|
|
|
void
|
|
decode_win_idma_setup(void)
|
|
{
|
|
uint32_t br, sz;
|
|
int i, j;
|
|
|
|
/*
|
|
* Disable and clear all IDMA windows, revoke protection for all channels
|
|
*/
|
|
for (i = 0; i < MV_WIN_IDMA_MAX; i++) {
|
|
|
|
idma_bare_write(i, 1);
|
|
win_idma_br_write(i, 0);
|
|
win_idma_sz_write(i, 0);
|
|
if (win_idma_can_remap(i) == 1)
|
|
win_idma_har_write(i, 0);
|
|
}
|
|
for (i = 0; i < MV_IDMA_CHAN_MAX; i++)
|
|
win_idma_cap_write(i, 0);
|
|
|
|
/*
|
|
* Set up access to all active DRAM banks
|
|
*/
|
|
for (i = 0; i < MV_WIN_DDR_MAX; i++)
|
|
if (ddr_is_active(i)) {
|
|
br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i);
|
|
sz = ((ddr_size(i) - 1) & 0xffff0000);
|
|
|
|
/* Place DDR entries in non-remapped windows */
|
|
for (j = 0; j < MV_WIN_IDMA_MAX; j++)
|
|
if (win_idma_can_remap(j) != 1 &&
|
|
idma_bare_read(j) == 1) {
|
|
|
|
/* Configure window */
|
|
win_idma_br_write(j, br);
|
|
win_idma_sz_write(j, sz);
|
|
|
|
/* Set protection RW on all channels */
|
|
idma_set_prot(j, 0x3);
|
|
|
|
/* Enable window */
|
|
idma_bare_write(j, 0);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Remaining targets -- from statically defined table
|
|
*/
|
|
for (i = 0; i < idma_wins_no; i++)
|
|
if (idma_wins[i].target > 0) {
|
|
br = (idma_wins[i].base & 0xffff0000) |
|
|
(idma_wins[i].attr << 8) | idma_wins[i].target;
|
|
sz = ((idma_wins[i].size - 1) & 0xffff0000);
|
|
|
|
/* Set the first free IDMA window */
|
|
for (j = 0; j < MV_WIN_IDMA_MAX; j++) {
|
|
if (idma_bare_read(j) == 0)
|
|
continue;
|
|
|
|
/* Configure window */
|
|
win_idma_br_write(j, br);
|
|
win_idma_sz_write(j, sz);
|
|
if (win_idma_can_remap(j) &&
|
|
idma_wins[j].remap >= 0)
|
|
win_idma_har_write(j, idma_wins[j].remap);
|
|
|
|
/* Set protection RW on all channels */
|
|
idma_set_prot(j, 0x3);
|
|
|
|
/* Enable window */
|
|
idma_bare_write(j, 0);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
int
|
|
decode_win_idma_valid(void)
|
|
{
|
|
const struct decode_win *wintab;
|
|
int c, i, j, rv;
|
|
uint32_t b, e, s;
|
|
|
|
if (idma_wins_no > MV_WIN_IDMA_MAX) {
|
|
printf("IDMA windows: too many entries: %d\n", idma_wins_no);
|
|
return (-1);
|
|
}
|
|
for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++)
|
|
if (ddr_is_active(i))
|
|
c++;
|
|
|
|
if (idma_wins_no > (MV_WIN_IDMA_MAX - c)) {
|
|
printf("IDMA windows: too many entries: %d, available: %d\n",
|
|
idma_wins_no, MV_WIN_IDMA_MAX - c);
|
|
return (-1);
|
|
}
|
|
|
|
wintab = idma_wins;
|
|
rv = 1;
|
|
for (i = 0; i < idma_wins_no; i++, wintab++) {
|
|
|
|
if (wintab->target == 0) {
|
|
printf("IDMA window#%d: DDR target window is not "
|
|
"supposed to be reprogrammed!\n", i);
|
|
rv = 0;
|
|
}
|
|
|
|
if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) {
|
|
printf("IDMA window#%d: not capable of remapping, but "
|
|
"val 0x%08x defined\n", i, wintab->remap);
|
|
rv = 0;
|
|
}
|
|
|
|
s = wintab->size;
|
|
b = wintab->base;
|
|
e = b + s - 1;
|
|
if (s > (0xFFFFFFFF - b + 1)) {
|
|
/* XXX this boundary check should account for 64bit and
|
|
* remapping.. */
|
|
printf("IDMA window#%d: no space for size 0x%08x at "
|
|
"0x%08x\n", i, s, b);
|
|
rv = 0;
|
|
continue;
|
|
}
|
|
|
|
j = decode_win_overlap(i, idma_wins_no, &idma_wins[0]);
|
|
if (j >= 0) {
|
|
printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps "
|
|
"with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
|
|
idma_wins[j].base,
|
|
idma_wins[j].base + idma_wins[j].size - 1);
|
|
rv = 0;
|
|
}
|
|
}
|
|
|
|
return (rv);
|
|
}
|
|
|
|
void
|
|
decode_win_idma_dump(void)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < MV_WIN_IDMA_MAX; i++) {
|
|
printf("IDMA window#%d: b 0x%08x, s 0x%08x", i,
|
|
win_idma_br_read(i), win_idma_sz_read(i));
|
|
|
|
if (win_idma_can_remap(i))
|
|
printf(", ha 0x%08x", win_idma_har_read(i));
|
|
|
|
printf("\n");
|
|
}
|
|
for (i = 0; i < MV_IDMA_CHAN_MAX; i++)
|
|
printf("IDMA channel#%d: ap 0x%08x\n", i,
|
|
win_idma_cap_read(i));
|
|
printf("IDMA windows: bare 0x%08x\n", win_idma_bare_read());
|
|
}
|
|
#else
|
|
|
|
/* Provide dummy functions to satisfy the build for SoCs not equipped with IDMA */
|
|
int
|
|
decode_win_idma_valid(void)
|
|
{
|
|
|
|
return (1);
|
|
}
|
|
|
|
void
|
|
decode_win_idma_setup(void)
|
|
{
|
|
}
|
|
|
|
void
|
|
decode_win_idma_dump(void)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
/**************************************************************************
|
|
* XOR windows routines
|
|
**************************************************************************/
|
|
#if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
|
|
static int
|
|
xor_ctrl_read(int i, int c, int e)
|
|
{
|
|
uint32_t v;
|
|
v = win_xor_ctrl_read(c, e);
|
|
v &= (1 << i);
|
|
|
|
return (v >> i);
|
|
}
|
|
|
|
static void
|
|
xor_ctrl_write(int i, int c, int e, int val)
|
|
{
|
|
uint32_t v;
|
|
|
|
v = win_xor_ctrl_read(c, e);
|
|
v &= ~(1 << i);
|
|
v |= (val << i);
|
|
win_xor_ctrl_write(c, e, v);
|
|
}
|
|
|
|
/*
|
|
* Set channel protection 'val' for window 'w' on channel 'c'
|
|
*/
|
|
|
|
static void
|
|
xor_chan_write(int c, int e, int w, int val)
|
|
{
|
|
uint32_t v;
|
|
|
|
v = win_xor_ctrl_read(c, e);
|
|
v &= ~(0x3 << (w * 2 + 16));
|
|
v |= (val << (w * 2 + 16));
|
|
win_xor_ctrl_write(c, e, v);
|
|
}
|
|
|
|
/*
|
|
* Set protection 'val' on all channels for window 'w' on engine 'e'
|
|
*/
|
|
static void
|
|
xor_set_prot(int w, int e, int val)
|
|
{
|
|
int c;
|
|
|
|
for (c = 0; c < MV_XOR_CHAN_MAX; c++)
|
|
xor_chan_write(c, e, w, val);
|
|
}
|
|
|
|
static int
|
|
win_xor_can_remap(int i)
|
|
{
|
|
|
|
/* XOR decode windows 0-3 have remap capability */
|
|
if (i < 4)
|
|
return (1);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
xor_max_eng(void)
|
|
{
|
|
uint32_t dev, rev;
|
|
|
|
soc_id(&dev, &rev);
|
|
if (dev == MV_DEV_88F6281)
|
|
return (2);
|
|
else if ((dev == MV_DEV_MV78100) || (dev == MV_DEV_MV78100_Z0))
|
|
return (1);
|
|
else
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
xor_active_dram(int c, int e, int *window)
|
|
{
|
|
uint32_t br, sz;
|
|
int i, m, w;
|
|
|
|
/*
|
|
* Set up access to all active DRAM banks
|
|
*/
|
|
m = xor_max_eng();
|
|
for (i = 0; i < m; i++)
|
|
if (ddr_is_active(i)) {
|
|
br = ddr_base(i) | (ddr_attr(i) << 8) |
|
|
ddr_target(i);
|
|
sz = ((ddr_size(i) - 1) & 0xffff0000);
|
|
|
|
/* Place DDR entries in non-remapped windows */
|
|
for (w = 0; w < MV_WIN_XOR_MAX; w++)
|
|
if (win_xor_can_remap(w) != 1 &&
|
|
(xor_ctrl_read(w, c, e) == 0) &&
|
|
w > *window) {
|
|
/* Configure window */
|
|
win_xor_br_write(w, e, br);
|
|
win_xor_sz_write(w, e, sz);
|
|
|
|
/* Set protection RW on all channels */
|
|
xor_set_prot(w, e, 0x3);
|
|
|
|
/* Enable window */
|
|
xor_ctrl_write(w, c, e, 1);
|
|
(*window)++;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
decode_win_xor_setup(void)
|
|
{
|
|
uint32_t br, sz;
|
|
int i, j, z, e = 1, m, window;
|
|
|
|
/*
|
|
* Disable and clear all XOR windows, revoke protection for all
|
|
* channels
|
|
*/
|
|
m = xor_max_eng();
|
|
for (j = 0; j < m; j++, e--) {
|
|
|
|
/* Number of non-remaped windows */
|
|
window = MV_XOR_NON_REMAP - 1;
|
|
|
|
for (i = 0; i < MV_WIN_XOR_MAX; i++) {
|
|
win_xor_br_write(i, e, 0);
|
|
win_xor_sz_write(i, e, 0);
|
|
}
|
|
|
|
if (win_xor_can_remap(i) == 1)
|
|
win_xor_har_write(i, e, 0);
|
|
|
|
for (i = 0; i < MV_XOR_CHAN_MAX; i++) {
|
|
win_xor_ctrl_write(i, e, 0);
|
|
xor_active_dram(i, e, &window);
|
|
}
|
|
|
|
/*
|
|
* Remaining targets -- from a statically defined table
|
|
*/
|
|
for (i = 0; i < xor_wins_no; i++)
|
|
if (xor_wins[i].target > 0) {
|
|
br = (xor_wins[i].base & 0xffff0000) |
|
|
(xor_wins[i].attr << 8) |
|
|
xor_wins[i].target;
|
|
sz = ((xor_wins[i].size - 1) & 0xffff0000);
|
|
|
|
/* Set the first free XOR window */
|
|
for (z = 0; z < MV_WIN_XOR_MAX; z++) {
|
|
if (xor_ctrl_read(z, 0, e) &&
|
|
xor_ctrl_read(z, 1, e))
|
|
continue;
|
|
|
|
/* Configure window */
|
|
win_xor_br_write(z, e, br);
|
|
win_xor_sz_write(z, e, sz);
|
|
if (win_xor_can_remap(z) &&
|
|
xor_wins[z].remap >= 0)
|
|
win_xor_har_write(z, e,
|
|
xor_wins[z].remap);
|
|
|
|
/* Set protection RW on all channels */
|
|
xor_set_prot(z, e, 0x3);
|
|
|
|
/* Enable window */
|
|
xor_ctrl_write(z, 0, e, 1);
|
|
xor_ctrl_write(z, 1, e, 1);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
int
|
|
decode_win_xor_valid(void)
|
|
{
|
|
const struct decode_win *wintab;
|
|
int c, i, j, rv;
|
|
uint32_t b, e, s;
|
|
|
|
if (xor_wins_no > MV_WIN_XOR_MAX) {
|
|
printf("XOR windows: too many entries: %d\n", xor_wins_no);
|
|
return (-1);
|
|
}
|
|
for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++)
|
|
if (ddr_is_active(i))
|
|
c++;
|
|
|
|
if (xor_wins_no > (MV_WIN_XOR_MAX - c)) {
|
|
printf("XOR windows: too many entries: %d, available: %d\n",
|
|
xor_wins_no, MV_WIN_IDMA_MAX - c);
|
|
return (-1);
|
|
}
|
|
|
|
wintab = xor_wins;
|
|
rv = 1;
|
|
for (i = 0; i < xor_wins_no; i++, wintab++) {
|
|
|
|
if (wintab->target == 0) {
|
|
printf("XOR window#%d: DDR target window is not "
|
|
"supposed to be reprogrammed!\n", i);
|
|
rv = 0;
|
|
}
|
|
|
|
if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) {
|
|
printf("XOR window#%d: not capable of remapping, but "
|
|
"val 0x%08x defined\n", i, wintab->remap);
|
|
rv = 0;
|
|
}
|
|
|
|
s = wintab->size;
|
|
b = wintab->base;
|
|
e = b + s - 1;
|
|
if (s > (0xFFFFFFFF - b + 1)) {
|
|
/*
|
|
* XXX this boundary check should account for 64bit
|
|
* and remapping..
|
|
*/
|
|
printf("XOR window#%d: no space for size 0x%08x at "
|
|
"0x%08x\n", i, s, b);
|
|
rv = 0;
|
|
continue;
|
|
}
|
|
|
|
j = decode_win_overlap(i, xor_wins_no, &xor_wins[0]);
|
|
if (j >= 0) {
|
|
printf("XOR window#%d: (0x%08x - 0x%08x) overlaps "
|
|
"with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
|
|
xor_wins[j].base,
|
|
xor_wins[j].base + xor_wins[j].size - 1);
|
|
rv = 0;
|
|
}
|
|
}
|
|
|
|
return (rv);
|
|
}
|
|
|
|
void
|
|
decode_win_xor_dump(void)
|
|
{
|
|
int i, j;
|
|
int e = 1;
|
|
|
|
for (j = 0; j < xor_max_eng(); j++, e--) {
|
|
for (i = 0; i < MV_WIN_XOR_MAX; i++) {
|
|
printf("XOR window#%d: b 0x%08x, s 0x%08x", i,
|
|
win_xor_br_read(i, e), win_xor_sz_read(i, e));
|
|
|
|
if (win_xor_can_remap(i))
|
|
printf(", ha 0x%08x", win_xor_har_read(i, e));
|
|
|
|
printf("\n");
|
|
}
|
|
for (i = 0; i < MV_XOR_CHAN_MAX; i++)
|
|
printf("XOR control#%d: 0x%08x\n", i,
|
|
win_xor_ctrl_read(i, e));
|
|
}
|
|
}
|
|
|
|
#else
|
|
/* Provide dummy functions to satisfy the build for SoCs not equipped with XOR */
|
|
int
|
|
decode_win_xor_valid(void)
|
|
{
|
|
|
|
return (1);
|
|
}
|
|
|
|
void
|
|
decode_win_xor_setup(void)
|
|
{
|
|
}
|
|
|
|
void
|
|
decode_win_xor_dump(void)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
/**************************************************************************
|
|
* CESA TDMA windows routines
|
|
**************************************************************************/
|
|
#if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
|
|
/*
|
|
* Dump CESA TDMA decode windows.
|
|
*/
|
|
static void
|
|
decode_win_cesa_dump(void)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < MV_WIN_CESA_MAX; i++)
|
|
printf("CESA window#%d: c 0x%08x, b 0x%08x\n", i,
|
|
win_cesa_cr_read(i), win_cesa_br_read(i));
|
|
}
|
|
|
|
|
|
/*
|
|
* Set CESA TDMA decode windows.
|
|
*/
|
|
static void
|
|
decode_win_cesa_setup(void)
|
|
{
|
|
uint32_t br, cr;
|
|
int i, j;
|
|
|
|
/* Disable and clear all CESA windows */
|
|
for (i = 0; i < MV_WIN_CESA_MAX; i++) {
|
|
win_cesa_cr_write(i, 0);
|
|
win_cesa_br_write(i, 0);
|
|
}
|
|
|
|
/* Only access to active DRAM banks is required. */
|
|
for (i = 0; i < MV_WIN_DDR_MAX; i++)
|
|
if (ddr_is_active(i)) {
|
|
br = ddr_base(i);
|
|
cr = (((ddr_size(i) - 1) & 0xffff0000) |
|
|
(ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1);
|
|
|
|
/* Set the first available CESA window */
|
|
for (j = 0; j < MV_WIN_CESA_MAX; j++) {
|
|
if (win_cesa_cr_read(j) & 0x1)
|
|
continue;
|
|
|
|
win_cesa_br_write(j, br);
|
|
win_cesa_cr_write(j, cr);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Check CESA TDMA decode windows.
|
|
*/
|
|
static int
|
|
decode_win_cesa_valid(void)
|
|
{
|
|
|
|
return (decode_win_can_cover_ddr(MV_WIN_CESA_MAX));
|
|
}
|
|
#else
|
|
|
|
/*
|
|
* Provide dummy functions to satisfy the build for SoCs not equipped with
|
|
* CESA
|
|
*/
|
|
|
|
int
|
|
decode_win_cesa_valid(void)
|
|
{
|
|
|
|
return (1);
|
|
}
|
|
|
|
void
|
|
decode_win_cesa_setup(void)
|
|
{
|
|
}
|
|
|
|
void
|
|
decode_win_cesa_dump(void)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
/**************************************************************************
|
|
* SATA windows routines
|
|
**************************************************************************/
|
|
static void
|
|
decode_win_sata_setup(void)
|
|
{
|
|
uint32_t cr, br;
|
|
int i, j;
|
|
|
|
for (i = 0; i < MV_WIN_SATA_MAX; i++) {
|
|
win_sata_cr_write(i, 0);
|
|
win_sata_br_write(i, 0);
|
|
}
|
|
|
|
for (i = 0; i < MV_WIN_DDR_MAX; i++)
|
|
if (ddr_is_active(i)) {
|
|
cr = ((ddr_size(i) - 1) & 0xffff0000) |
|
|
(ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1;
|
|
br = ddr_base(i);
|
|
|
|
/* Use the first available SATA window */
|
|
for (j = 0; j < MV_WIN_SATA_MAX; j++) {
|
|
if ((win_sata_cr_read(j) & 1) != 0)
|
|
continue;
|
|
|
|
win_sata_br_write(j, br);
|
|
win_sata_cr_write(j, cr);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
static int
|
|
decode_win_sata_valid(void)
|
|
{
|
|
uint32_t dev, rev;
|
|
|
|
soc_id(&dev, &rev);
|
|
if (dev == MV_DEV_88F5281)
|
|
return (1);
|
|
|
|
return (decode_win_can_cover_ddr(MV_WIN_SATA_MAX));
|
|
}
|