a48f5e1ffa
actual numbers would help debugging (also, `MSR' and `ACPI' are standard abbreviations and thus should be properly capitalized) - Rephrase unsupported AMD CPUs message and wrap as an overly long line: `sorry' 1) is wrongly spelled after period (starts with a small letter) and 2) carries emotional "tinge" that is unnecessary and even bogus in debug message; `implemented' is not the best word as `supported' suits better in this context - Improve readability when reporting resulted P-state transition (debug) Approved by: jhb
513 lines
13 KiB
C
513 lines
13 KiB
C
/*-
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* Copyright (c) 2005 Nate Lawson
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* Copyright (c) 2004 Colin Percival
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* Copyright (c) 2004-2005 Bruno Durcot
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* Copyright (c) 2004 FUKUDA Nobuhiko
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* Copyright (c) 2009 Michael Reifenberger
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* Copyright (c) 2009 Norikatsu Shigemura
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* Copyright (c) 2008-2009 Gen Otsuji
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*
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* This code is depending on kern_cpu.c, est.c, powernow.c, p4tcc.c, smist.c
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* in various parts. The authors of these files are Nate Lawson,
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* Colin Percival, Bruno Durcot, and FUKUDA Nobuhiko.
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* This code contains patches by Michael Reifenberger and Norikatsu Shigemura.
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* Thank you.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted providing that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* For more info:
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* BIOS and Kernel Developer's Guide(BKDG) for AMD Family 10h Processors
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* 31116 Rev 3.20 February 04, 2009
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* BIOS and Kernel Developer's Guide(BKDG) for AMD Family 11h Processors
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* 41256 Rev 3.00 - July 07, 2008
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/cpu.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/proc.h>
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#include <sys/pcpu.h>
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#include <sys/smp.h>
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#include <sys/sched.h>
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#include <machine/md_var.h>
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#include <machine/cputypes.h>
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#include <machine/specialreg.h>
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#include <contrib/dev/acpica/include/acpi.h>
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#include <dev/acpica/acpivar.h>
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#include "acpi_if.h"
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#include "cpufreq_if.h"
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#define MSR_AMD_10H_11H_LIMIT 0xc0010061
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#define MSR_AMD_10H_11H_CONTROL 0xc0010062
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#define MSR_AMD_10H_11H_STATUS 0xc0010063
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#define MSR_AMD_10H_11H_CONFIG 0xc0010064
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#define AMD_10H_11H_MAX_STATES 16
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/* for MSR_AMD_10H_11H_LIMIT C001_0061 */
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#define AMD_10H_11H_GET_PSTATE_MAX_VAL(msr) (((msr) >> 4) & 0x7)
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#define AMD_10H_11H_GET_PSTATE_LIMIT(msr) (((msr)) & 0x7)
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/* for MSR_AMD_10H_11H_CONFIG 10h:C001_0064:68 / 11h:C001_0064:6B */
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#define AMD_10H_11H_CUR_VID(msr) (((msr) >> 9) & 0x7F)
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#define AMD_10H_11H_CUR_DID(msr) (((msr) >> 6) & 0x07)
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#define AMD_10H_11H_CUR_FID(msr) ((msr) & 0x3F)
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#define HWPSTATE_DEBUG(dev, msg...) \
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do{ \
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if(hwpstate_verbose) \
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device_printf(dev, msg); \
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}while(0)
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struct hwpstate_setting {
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int freq; /* CPU clock in Mhz or 100ths of a percent. */
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int volts; /* Voltage in mV. */
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int power; /* Power consumed in mW. */
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int lat; /* Transition latency in us. */
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int pstate_id; /* P-State id */
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};
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struct hwpstate_softc {
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device_t dev;
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struct hwpstate_setting hwpstate_settings[AMD_10H_11H_MAX_STATES];
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int cfnum;
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};
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static void hwpstate_identify(driver_t *driver, device_t parent);
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static int hwpstate_probe(device_t dev);
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static int hwpstate_attach(device_t dev);
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static int hwpstate_detach(device_t dev);
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static int hwpstate_set(device_t dev, const struct cf_setting *cf);
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static int hwpstate_get(device_t dev, struct cf_setting *cf);
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static int hwpstate_settings(device_t dev, struct cf_setting *sets, int *count);
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static int hwpstate_type(device_t dev, int *type);
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static int hwpstate_shutdown(device_t dev);
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static int hwpstate_features(driver_t *driver, u_int *features);
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static int hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev);
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static int hwpstate_get_info_from_msr(device_t dev);
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static int hwpstate_goto_pstate(device_t dev, int pstate_id);
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static int hwpstate_verbose = 0;
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SYSCTL_INT(_debug, OID_AUTO, hwpstate_verbose, CTLFLAG_RWTUN,
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&hwpstate_verbose, 0, "Debug hwpstate");
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static device_method_t hwpstate_methods[] = {
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/* Device interface */
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DEVMETHOD(device_identify, hwpstate_identify),
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DEVMETHOD(device_probe, hwpstate_probe),
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DEVMETHOD(device_attach, hwpstate_attach),
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DEVMETHOD(device_detach, hwpstate_detach),
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DEVMETHOD(device_shutdown, hwpstate_shutdown),
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/* cpufreq interface */
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DEVMETHOD(cpufreq_drv_set, hwpstate_set),
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DEVMETHOD(cpufreq_drv_get, hwpstate_get),
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DEVMETHOD(cpufreq_drv_settings, hwpstate_settings),
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DEVMETHOD(cpufreq_drv_type, hwpstate_type),
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/* ACPI interface */
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DEVMETHOD(acpi_get_features, hwpstate_features),
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{0, 0}
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};
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static devclass_t hwpstate_devclass;
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static driver_t hwpstate_driver = {
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"hwpstate",
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hwpstate_methods,
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sizeof(struct hwpstate_softc),
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};
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DRIVER_MODULE(hwpstate, cpu, hwpstate_driver, hwpstate_devclass, 0, 0);
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/*
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* Go to Px-state on all cpus considering the limit.
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*/
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static int
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hwpstate_goto_pstate(device_t dev, int pstate)
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{
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int i;
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uint64_t msr;
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int j;
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int limit;
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int id = pstate;
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int error;
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/* get the current pstate limit */
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msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
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limit = AMD_10H_11H_GET_PSTATE_LIMIT(msr);
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if(limit > id)
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id = limit;
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/*
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* We are going to the same Px-state on all cpus.
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* Probably should take _PSD into account.
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*/
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error = 0;
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CPU_FOREACH(i) {
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/* Bind to each cpu. */
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thread_lock(curthread);
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sched_bind(curthread, i);
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thread_unlock(curthread);
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HWPSTATE_DEBUG(dev, "setting P%d-state on cpu%d\n",
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id, PCPU_GET(cpuid));
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/* Go To Px-state */
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wrmsr(MSR_AMD_10H_11H_CONTROL, id);
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}
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CPU_FOREACH(i) {
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/* Bind to each cpu. */
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thread_lock(curthread);
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sched_bind(curthread, i);
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thread_unlock(curthread);
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/* wait loop (100*100 usec is enough ?) */
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for(j = 0; j < 100; j++){
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/* get the result. not assure msr=id */
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msr = rdmsr(MSR_AMD_10H_11H_STATUS);
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if(msr == id){
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break;
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}
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DELAY(100);
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}
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HWPSTATE_DEBUG(dev, "result: P%d-state on cpu%d\n",
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(int)msr, PCPU_GET(cpuid));
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if (msr != id) {
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HWPSTATE_DEBUG(dev, "error: loop is not enough.\n");
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error = ENXIO;
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}
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}
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thread_lock(curthread);
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sched_unbind(curthread);
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thread_unlock(curthread);
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return (error);
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}
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static int
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hwpstate_set(device_t dev, const struct cf_setting *cf)
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{
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struct hwpstate_softc *sc;
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struct hwpstate_setting *set;
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int i;
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if (cf == NULL)
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return (EINVAL);
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sc = device_get_softc(dev);
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set = sc->hwpstate_settings;
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for (i = 0; i < sc->cfnum; i++)
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if (CPUFREQ_CMP(cf->freq, set[i].freq))
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break;
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if (i == sc->cfnum)
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return (EINVAL);
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return (hwpstate_goto_pstate(dev, set[i].pstate_id));
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}
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static int
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hwpstate_get(device_t dev, struct cf_setting *cf)
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{
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struct hwpstate_softc *sc;
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struct hwpstate_setting set;
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uint64_t msr;
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sc = device_get_softc(dev);
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if (cf == NULL)
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return (EINVAL);
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msr = rdmsr(MSR_AMD_10H_11H_STATUS);
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if(msr >= sc->cfnum)
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return (EINVAL);
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set = sc->hwpstate_settings[msr];
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cf->freq = set.freq;
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cf->volts = set.volts;
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cf->power = set.power;
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cf->lat = set.lat;
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cf->dev = dev;
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return (0);
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}
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static int
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hwpstate_settings(device_t dev, struct cf_setting *sets, int *count)
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{
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struct hwpstate_softc *sc;
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struct hwpstate_setting set;
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int i;
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if (sets == NULL || count == NULL)
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return (EINVAL);
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sc = device_get_softc(dev);
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if (*count < sc->cfnum)
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return (E2BIG);
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for (i = 0; i < sc->cfnum; i++, sets++) {
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set = sc->hwpstate_settings[i];
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sets->freq = set.freq;
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sets->volts = set.volts;
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sets->power = set.power;
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sets->lat = set.lat;
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sets->dev = dev;
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}
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*count = sc->cfnum;
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return (0);
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}
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static int
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hwpstate_type(device_t dev, int *type)
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{
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if (type == NULL)
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return (EINVAL);
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*type = CPUFREQ_TYPE_ABSOLUTE;
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return (0);
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}
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static void
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hwpstate_identify(driver_t *driver, device_t parent)
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{
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if (device_find_child(parent, "hwpstate", -1) != NULL)
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return;
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if (cpu_vendor_id != CPU_VENDOR_AMD || CPUID_TO_FAMILY(cpu_id) < 0x10)
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return;
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/*
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* Check if hardware pstate enable bit is set.
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*/
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if ((amd_pminfo & AMDPM_HW_PSTATE) == 0) {
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HWPSTATE_DEBUG(parent, "hwpstate enable bit is not set.\n");
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return;
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}
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if (resource_disabled("hwpstate", 0))
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return;
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if (BUS_ADD_CHILD(parent, 10, "hwpstate", -1) == NULL)
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device_printf(parent, "hwpstate: add child failed\n");
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}
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static int
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hwpstate_probe(device_t dev)
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{
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struct hwpstate_softc *sc;
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device_t perf_dev;
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uint64_t msr;
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int error, type;
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/*
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* Only hwpstate0.
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* It goes well with acpi_throttle.
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*/
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if (device_get_unit(dev) != 0)
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return (ENXIO);
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sc = device_get_softc(dev);
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sc->dev = dev;
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/*
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* Check if acpi_perf has INFO only flag.
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*/
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perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
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error = TRUE;
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if (perf_dev && device_is_attached(perf_dev)) {
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error = CPUFREQ_DRV_TYPE(perf_dev, &type);
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if (error == 0) {
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if ((type & CPUFREQ_FLAG_INFO_ONLY) == 0) {
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/*
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* If acpi_perf doesn't have INFO_ONLY flag,
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* it will take care of pstate transitions.
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*/
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HWPSTATE_DEBUG(dev, "acpi_perf will take care of pstate transitions.\n");
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return (ENXIO);
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} else {
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/*
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* If acpi_perf has INFO_ONLY flag, (_PCT has FFixedHW)
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* we can get _PSS info from acpi_perf
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* without going into ACPI.
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*/
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HWPSTATE_DEBUG(dev, "going to fetch info from acpi_perf\n");
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error = hwpstate_get_info_from_acpi_perf(dev, perf_dev);
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}
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}
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}
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if (error == 0) {
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/*
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* Now we get _PSS info from acpi_perf without error.
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* Let's check it.
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*/
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msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
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if (sc->cfnum != 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr)) {
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HWPSTATE_DEBUG(dev, "MSR (%jd) and ACPI _PSS (%d)"
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" count mismatch\n", (intmax_t)msr, sc->cfnum);
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error = TRUE;
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}
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}
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/*
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* If we cannot get info from acpi_perf,
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* Let's get info from MSRs.
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*/
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if (error)
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error = hwpstate_get_info_from_msr(dev);
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if (error)
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return (error);
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device_set_desc(dev, "Cool`n'Quiet 2.0");
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return (0);
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}
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static int
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hwpstate_attach(device_t dev)
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{
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return (cpufreq_register(dev));
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}
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static int
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hwpstate_get_info_from_msr(device_t dev)
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{
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struct hwpstate_softc *sc;
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struct hwpstate_setting *hwpstate_set;
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uint64_t msr;
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int family, i, fid, did;
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family = CPUID_TO_FAMILY(cpu_id);
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sc = device_get_softc(dev);
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/* Get pstate count */
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msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
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sc->cfnum = 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr);
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hwpstate_set = sc->hwpstate_settings;
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for (i = 0; i < sc->cfnum; i++) {
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msr = rdmsr(MSR_AMD_10H_11H_CONFIG + i);
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if ((msr & ((uint64_t)1 << 63)) == 0) {
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HWPSTATE_DEBUG(dev, "msr is not valid.\n");
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return (ENXIO);
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}
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did = AMD_10H_11H_CUR_DID(msr);
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fid = AMD_10H_11H_CUR_FID(msr);
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/* Convert fid/did to frequency. */
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switch(family) {
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case 0x11:
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hwpstate_set[i].freq = (100 * (fid + 0x08)) >> did;
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break;
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case 0x10:
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case 0x12:
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case 0x15:
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case 0x16:
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hwpstate_set[i].freq = (100 * (fid + 0x10)) >> did;
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break;
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default:
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HWPSTATE_DEBUG(dev, "get_info_from_msr: AMD family"
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" 0x%02x CPUs are not supported yet\n", family);
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return (ENXIO);
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}
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hwpstate_set[i].pstate_id = i;
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/* There was volts calculation, but deleted it. */
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hwpstate_set[i].volts = CPUFREQ_VAL_UNKNOWN;
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hwpstate_set[i].power = CPUFREQ_VAL_UNKNOWN;
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hwpstate_set[i].lat = CPUFREQ_VAL_UNKNOWN;
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}
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return (0);
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}
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static int
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hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev)
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{
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struct hwpstate_softc *sc;
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struct cf_setting *perf_set;
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struct hwpstate_setting *hwpstate_set;
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int count, error, i;
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perf_set = malloc(MAX_SETTINGS * sizeof(*perf_set), M_TEMP, M_NOWAIT);
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if (perf_set == NULL) {
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HWPSTATE_DEBUG(dev, "nomem\n");
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return (ENOMEM);
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}
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/*
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* Fetch settings from acpi_perf.
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* Now it is attached, and has info only flag.
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*/
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count = MAX_SETTINGS;
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error = CPUFREQ_DRV_SETTINGS(perf_dev, perf_set, &count);
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if (error) {
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HWPSTATE_DEBUG(dev, "error: CPUFREQ_DRV_SETTINGS.\n");
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goto out;
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}
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sc = device_get_softc(dev);
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sc->cfnum = count;
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hwpstate_set = sc->hwpstate_settings;
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for (i = 0; i < count; i++) {
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if (i == perf_set[i].spec[0]) {
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hwpstate_set[i].pstate_id = i;
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hwpstate_set[i].freq = perf_set[i].freq;
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hwpstate_set[i].volts = perf_set[i].volts;
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hwpstate_set[i].power = perf_set[i].power;
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hwpstate_set[i].lat = perf_set[i].lat;
|
|
} else {
|
|
HWPSTATE_DEBUG(dev, "ACPI _PSS object mismatch.\n");
|
|
error = ENXIO;
|
|
goto out;
|
|
}
|
|
}
|
|
out:
|
|
if (perf_set)
|
|
free(perf_set, M_TEMP);
|
|
return (error);
|
|
}
|
|
|
|
static int
|
|
hwpstate_detach(device_t dev)
|
|
{
|
|
|
|
hwpstate_goto_pstate(dev, 0);
|
|
return (cpufreq_unregister(dev));
|
|
}
|
|
|
|
static int
|
|
hwpstate_shutdown(device_t dev)
|
|
{
|
|
|
|
/* hwpstate_goto_pstate(dev, 0); */
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
hwpstate_features(driver_t *driver, u_int *features)
|
|
{
|
|
|
|
/* Notify the ACPI CPU that we support direct access to MSRs */
|
|
*features = ACPI_CAP_PERF_MSRS;
|
|
return (0);
|
|
}
|