ab418d7db3
Promise Ultra100 / Fasttrak100 HighPoint HPT370 controllers (fx Abit KA7-100 onboard ctrl, Abit HotRod 100) Intel ICH2 (Intel 815E based motherboards) So far I can read >90MB/s on the Promise and the HPT370. I can write >64MB/s on the promise and >50MB/s on the HPT370 so it seems writing is still done in ATA66 mode :( The ICH2 support is untested as of yet...
339 lines
13 KiB
C
339 lines
13 KiB
C
/*-
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* Copyright (c) 1998,1999,2000 Søren Schmidt
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/* ATA register defines */
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#define ATA_DATA 0x00 /* data register */
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#define ATA_ERROR 0x01 /* (R) error register */
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#define ATA_E_NM 0x02 /* no media */
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#define ATA_E_ABORT 0x04 /* command aborted */
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#define ATA_E_MCR 0x08 /* media change request */
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#define ATA_E_IDNF 0x10 /* ID not found */
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#define ATA_E_MC 0x20 /* media changed */
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#define ATA_E_UNC 0x40 /* uncorrectable data */
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#define ATA_E_ICRC 0x80 /* UDMA crc error */
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#define ATA_FEATURE 0x01 /* (W) feature register */
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#define ATA_F_DMA 0x01 /* enable DMA */
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#define ATA_F_OVL 0x02 /* enable overlap */
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#define ATA_COUNT 0x02 /* (W) sector count */
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#define ATA_IREASON 0x02 /* (R) interrupt reason */
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#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
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#define ATA_I_IN 0x02 /* read (1) | write (0) */
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#define ATA_I_RELEASE 0x04 /* released bus (1) */
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#define ATA_I_TAGMASK 0xf8 /* tag mask */
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#define ATA_SECTOR 0x03 /* sector # */
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#define ATA_CYL_LSB 0x04 /* cylinder# LSB */
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#define ATA_CYL_MSB 0x05 /* cylinder# MSB */
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#define ATA_DRIVE 0x06 /* Sector/Drive/Head register */
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#define ATA_D_LBA 0x40 /* use LBA adressing */
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#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
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#define ATA_CMD 0x07 /* command register */
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#define ATA_C_ATAPI_RESET 0x08 /* reset ATAPI device */
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#define ATA_C_READ 0x20 /* read command */
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#define ATA_C_WRITE 0x30 /* write command */
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#define ATA_C_PACKET_CMD 0xa0 /* packet command */
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#define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/
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#define ATA_C_READ_MUL 0xc4 /* read multi command */
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#define ATA_C_WRITE_MUL 0xc5 /* write multi command */
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#define ATA_C_SET_MULTI 0xc6 /* set multi size command */
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#define ATA_C_READ_DMA 0xc8 /* read w/DMA command */
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#define ATA_C_WRITE_DMA 0xca /* write w/DMA command */
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#define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */
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#define ATA_C_SETFEATURES 0xef /* features command */
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#define ATA_C_F_SETXFER 0x03 /* set transfer mode */
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#define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */
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#define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */
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#define ATA_STATUS 0x07 /* status register */
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#define ATA_S_ERROR 0x01 /* error */
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#define ATA_S_INDEX 0x02 /* index */
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#define ATA_S_CORR 0x04 /* data corrected */
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#define ATA_S_DRQ 0x08 /* data request */
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#define ATA_S_DSC 0x10 /* drive seek completed */
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#define ATA_S_SERVICE 0x10 /* drive needs service */
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#define ATA_S_DWF 0x20 /* drive write fault */
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#define ATA_S_DMA 0x20 /* DMA ready */
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#define ATA_S_READY 0x40 /* drive ready */
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#define ATA_S_BUSY 0x80 /* busy */
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#define ATA_ALTPORT 0x206 /* alternate status register */
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#define ATA_ALTPORT_PCCARD 0x8 /* ditto on PCCARD devices */
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#define ATA_A_IDS 0x02 /* disable interrupts */
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#define ATA_A_RESET 0x04 /* RESET controller */
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#define ATA_A_4BIT 0x08 /* 4 head bits */
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#define ATA_ALTIOSIZE 0x01
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/* misc defines */
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#define ATA_MASTER 0x00
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#define ATA_SLAVE 0x10
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#define ATA_IOSIZE 0x08
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#define ATA_OP_FINISHED 0x00
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#define ATA_OP_CONTINUES 0x01
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#define ATA_DEV(unit) ((unit == ATA_MASTER) ? 0 : 1)
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#define ATA_PARAM(scp, unit) scp->dev_param[ATA_DEV(unit)]
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/* busmaster DMA related defines */
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#define ATA_BM_OFFSET1 0x08
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#define ATA_DMA_ENTRIES 256
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#define ATA_DMA_EOT 0x80000000
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#define ATA_BMCMD_PORT 0x00
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#define ATA_BMCMD_START_STOP 0x01
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#define ATA_BMCMD_WRITE_READ 0x08
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#define ATA_BMSTAT_PORT 0x02
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#define ATA_BMSTAT_ACTIVE 0x01
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#define ATA_BMSTAT_ERROR 0x02
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#define ATA_BMSTAT_INTERRUPT 0x04
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#define ATA_BMSTAT_MASK 0x07
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#define ATA_BMSTAT_DMA_MASTER 0x20
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#define ATA_BMSTAT_DMA_SLAVE 0x40
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#define ATA_BMSTAT_DMA_SIMPLEX 0x80
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#define ATA_BMDTP_PORT 0x04
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#define ATA_BMIOSIZE 0x20
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/* structure for holding DMA address data */
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struct ata_dmaentry {
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u_int32_t base;
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u_int32_t count;
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};
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/* ATA/ATAPI device parameter information */
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struct ata_params {
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u_int8_t cmdsize :2; /* packet command size */
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#define ATAPI_PSIZE_12 0 /* 12 bytes */
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#define ATAPI_PSIZE_16 1 /* 16 bytes */
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u_int8_t :3;
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u_int8_t drqtype :2; /* DRQ type */
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#define ATAPI_DRQT_MPROC 0 /* cpu 3 ms delay */
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#define ATAPI_DRQT_INTR 1 /* intr 10 ms delay */
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#define ATAPI_DRQT_ACCEL 2 /* accel 50 us delay */
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u_int8_t removable :1; /* device is removable */
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u_int8_t device_type :5; /* device type */
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#define ATAPI_TYPE_DIRECT 0 /* disk/floppy */
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#define ATAPI_TYPE_TAPE 1 /* streaming tape */
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#define ATAPI_TYPE_CDROM 5 /* CD-ROM device */
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#define ATAPI_TYPE_OPTICAL 7 /* optical disk */
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u_int8_t :1;
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u_int8_t proto :2; /* command protocol */
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#define ATAPI_PROTO_ATAPI 2
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u_int16_t cylinders; /* number of cylinders */
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int16_t reserved2;
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u_int16_t heads; /* # heads */
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int16_t unfbytespertrk; /* # unformatted bytes/track */
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int16_t unfbytes; /* # unformatted bytes/sector */
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u_int16_t sectors; /* # sectors/track */
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int16_t vendorunique0[3];
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int8_t serial[20]; /* serial number */
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int16_t buffertype; /* buffer type */
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#define ATA_BT_SINGLEPORTSECTOR 1 /* 1 port, 1 sector buffer */
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#define ATA_BT_DUALPORTMULTI 2 /* 2 port, mult sector buffer */
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#define ATA_BT_DUALPORTMULTICACHE 3 /* above plus track cache */
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int16_t buffersize; /* buf size, 512-byte units */
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int16_t necc; /* ecc bytes appended */
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int8_t revision[8]; /* firmware revision */
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int8_t model[40]; /* model name */
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int8_t nsecperint; /* sectors per interrupt */
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int8_t vendorunique1;
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int16_t usedmovsd; /* double word read/write? */
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u_int8_t vendorcap; /* vendor capabilities */
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u_int8_t dmaflag :1; /* DMA supported - always 1 */
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u_int8_t lbaflag :1; /* LBA supported - always 1 */
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u_int8_t iordydis :1; /* IORDY may be disabled */
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u_int8_t iordyflag :1; /* IORDY supported */
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u_int8_t softreset :1; /* needs softreset when busy */
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u_int8_t stdby_ovlap :1; /* standby/overlap supported */
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u_int8_t queuing :1; /* supports queuing overlap */
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u_int8_t idmaflag :1; /* interleaved DMA supported */
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int16_t capvalidate; /* validation for above */
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int8_t vendorunique3;
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int8_t opiomode; /* PIO modes 0-2 */
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int8_t vendorunique4;
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int8_t odmamode; /* old DMA modes, not ATA-3 */
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int16_t atavalid; /* fields valid */
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#define ATA_FLAG_54_58 1 /* words 54-58 valid */
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#define ATA_FLAG_64_70 2 /* words 64-70 valid */
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#define ATA_FLAG_88 4 /* word 88 valid */
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int16_t currcyls;
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int16_t currheads;
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int16_t currsectors;
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int16_t currsize0;
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int16_t currsize1;
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int8_t currmultsect;
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int8_t multsectvalid;
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int32_t lbasize;
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int16_t sdmamodes; /* singleword DMA modes */
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int16_t wdmamodes; /* multiword DMA modes */
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int16_t apiomodes; /* advanced PIO modes */
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u_int16_t mwdmamin; /* min. M/W DMA time/word ns */
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u_int16_t mwdmarec; /* rec. M/W DMA time ns */
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u_int16_t pioblind; /* min. PIO cycle w/o flow */
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u_int16_t pioiordy; /* min. PIO cycle IORDY flow */
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int16_t reserved69;
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int16_t reserved70;
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u_int16_t rlsovlap; /* rel time (us) for overlap */
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u_int16_t rlsservice; /* rel time (us) for service */
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int16_t reserved73;
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int16_t reserved74;
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int16_t queuelen;
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int16_t reserved76;
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int16_t reserved77;
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int16_t reserved78;
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int16_t reserved79;
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int16_t versmajor;
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int16_t versminor;
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int16_t featsupp1;
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int16_t featsupp2;
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int16_t featsupp3;
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int16_t featenab1;
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int16_t featenab2;
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int16_t featenab3;
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int16_t udmamodes; /* UltraDMA modes */
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int16_t erasetime;
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int16_t enherasetime;
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int16_t apmlevel;
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int16_t masterpasswdrev;
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u_int16_t masterhwres :8;
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u_int16_t slavehwres :5;
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u_int16_t cblid :1;
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u_int16_t reserved93_1415 :2;
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int16_t reserved94[32];
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int16_t rmvstat;
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int16_t securstat;
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int16_t reserved129[30];
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int16_t cfapwrmode;
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int16_t reserved161[84];
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int16_t integrity;
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};
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/* structure describing an ATA device */
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struct ata_softc {
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struct device *dev; /* device handle */
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int32_t unit; /* unit on this controller */
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struct resource *r_io; /* io addr resource handle */
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struct resource *r_altio; /* altio addr resource handle */
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struct resource *r_bmio; /* bmio addr resource handle */
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struct resource *r_irq; /* interrupt of this channel */
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void *ih; /* interrupt handle */
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int32_t ioaddr; /* physical port addr */
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int32_t altioaddr; /* physical alt port addr */
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int32_t bmaddr; /* physical bus master port */
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int32_t chiptype; /* pciid of controller chip */
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struct ata_params *dev_param[2]; /* ptr to devices params */
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void *dev_softc[2]; /* ptr to devices softc's */
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struct ata_dmaentry *dmatab[2]; /* DMA transfer tables */
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int32_t mode[2]; /* transfer mode for devices */
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#define ATA_PIO 0x00
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#define ATA_PIO0 0x08
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#define ATA_PIO1 0x09
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#define ATA_PIO2 0x0a
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#define ATA_PIO3 0x0b
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#define ATA_PIO4 0x0c
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#define ATA_DMA 0x10
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#define ATA_WDMA2 0x22
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#define ATA_UDMA2 0x42
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#define ATA_UDMA4 0x44
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#define ATA_UDMA5 0x45
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int32_t flags; /* controller flags */
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#define ATA_DMA_ACTIVE 0x01
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#define ATA_ATAPI_DMA_RO 0x02
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#define ATA_USE_16BIT 0x04
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#define ATA_ATTACHED 0x08
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int32_t devices; /* what is present */
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#define ATA_ATA_MASTER 0x01
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#define ATA_ATA_SLAVE 0x02
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#define ATA_ATAPI_MASTER 0x04
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#define ATA_ATAPI_SLAVE 0x08
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u_int8_t status; /* last controller status */
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u_int8_t error; /* last controller error */
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int32_t active; /* active processing request */
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#define ATA_IDLE 0x0
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#define ATA_IMMEDIATE 0x1
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#define ATA_WAIT_INTR 0x2
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#define ATA_WAIT_READY 0x3
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#define ATA_ACTIVE 0x4
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#define ATA_ACTIVE_ATA 0x5
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#define ATA_ACTIVE_ATAPI 0x6
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#define ATA_REINITING 0x7
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TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */
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TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */
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void *running; /* currently running request */
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};
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/* To convert unit numbers to devices */
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extern devclass_t ata_devclass;
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/* public prototypes */
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void ata_start(struct ata_softc *);
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void ata_reset(struct ata_softc *, int32_t *);
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int32_t ata_reinit(struct ata_softc *);
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int32_t ata_wait(struct ata_softc *, int32_t, u_int8_t);
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int32_t ata_command(struct ata_softc *, int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, int32_t);
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int ata_printf(struct ata_softc *, int32_t, const char *, ...) __printflike(3, 4);
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int ata_get_lun(u_int32_t *);
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void ata_free_lun(u_int32_t *, int);
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int8_t *ata_mode2str(int32_t);
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int8_t ata_pio2mode(int32_t);
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int ata_pmode(struct ata_params *);
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int ata_wmode(struct ata_params *);
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int ata_umode(struct ata_params *);
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#if NPCI > 0
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int32_t ata_find_dev(device_t, int32_t, int32_t);
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#endif
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void ata_dmainit(struct ata_softc *, int32_t, int32_t, int32_t, int32_t);
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int32_t ata_dmasetup(struct ata_softc *, int32_t, int8_t *, int32_t, int32_t);
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void ata_dmastart(struct ata_softc *);
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int32_t ata_dmastatus(struct ata_softc *);
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int32_t ata_dmadone(struct ata_softc *);
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