eb8943b13e
- Require the APIC enumerators to explicitly enable mixed mode by calling ioapic_enable_mixed_mode(). Calling this function tells the apic driver that the PC-AT 8259A PICs are present and routable through the first I/O APIC via an ExtINT pin. The mptable enumerator always calls this function for now. The MADT enumerator only enables mixed mode if the PC-AT compatability flag is set in the MADT header. - Allow mixed mode to be enabled or disabled via a 'hw.apic.mixed_mode' tunable. By default this tunable is set to 1 (true). The kernel option NO_MIXED_MODE changes the default to 0 to preserve existing behavior, but adding 'hw.apic.mixed_mode=0' to loader.conf achieves the same effect. - Only use mixed mode to route IRQ 0 if it is both enabled by the APIC enumerator and activated by the loader tunable. Note that both conditions must be true, so if the APIC enumerator does not enable mixed mode, then you can't set the tunable to try to override the enumerator.
173 lines
6.4 KiB
C
173 lines
6.4 KiB
C
/*-
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* Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_APICVAR_H_
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#define _MACHINE_APICVAR_H_
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/*
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* Local && I/O APIC variable definitions.
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*/
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/*
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* Layout of local APIC interrupt vectors:
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*
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* 0xff (255) +-------------+
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* | | 15 (Spurious / IPIs / Local Interrupts)
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* 0xf0 (240) +-------------+
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* | | 14 (I/O Interrupts)
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* 0xe0 (224) +-------------+
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* | | 13 (I/O Interrupts)
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* 0xd0 (208) +-------------+
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* | | 12 (I/O Interrupts)
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* 0xc0 (192) +-------------+
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* | | 11 (I/O Interrupts)
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* 0xb0 (176) +-------------+
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* | | 10 (I/O Interrupts)
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* 0xa0 (160) +-------------+
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* | | 9 (I/O Interrupts)
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* 0x90 (144) +-------------+
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* | | 8 (I/O Interrupts / System Calls)
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* 0x80 (128) +-------------+
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* | | 7 (I/O Interrupts)
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* 0x70 (112) +-------------+
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* | | 6 (I/O Interrupts)
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* 0x60 (96) +-------------+
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* | | 5 (I/O Interrupts)
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* 0x50 (80) +-------------+
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* | | 4 (I/O Interrupts)
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* 0x40 (64) +-------------+
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* | | 3 (I/O Interrupts)
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* 0x30 (48) +-------------+
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* | | 2 (ATPIC Interrupts)
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* 0x20 (32) +-------------+
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* | | 1 (Exceptions, traps, faults, etc.)
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* 0x10 (16) +-------------+
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* | | 0 (Exceptions, traps, faults, etc.)
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* 0x00 (0) +-------------+
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*
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* Note: 0x80 needs to be handled specially and not allocated to an
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* I/O device!
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*/
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#define APIC_ID_ALL 0xff
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#define APIC_IO_INTS (IDT_IO_INTS + 16)
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#define APIC_NUM_IOINTS 192
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#define APIC_LOCAL_INTS 240
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#define APIC_TIMER_INT APIC_LOCAL_INTS
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#define APIC_ERROR_INT (APIC_LOCAL_INTS + 1)
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#define APIC_THERMAL_INT (APIC_LOCAL_INTS + 2)
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#define APIC_IPI_INTS (APIC_LOCAL_INTS + 3)
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#define IPI_AST APIC_IPI_INTS /* Generate software trap. */
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#define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs */
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#define IPI_INVLPG (APIC_IPI_INTS + 2)
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#define IPI_INVLRNG (APIC_IPI_INTS + 3)
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#define IPI_LAZYPMAP (APIC_IPI_INTS + 4) /* Lazy pmap release. */
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#define IPI_HARDCLOCK (APIC_IPI_INTS + 8) /* Inter-CPU clock handling. */
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#define IPI_STATCLOCK (APIC_IPI_INTS + 9)
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#define IPI_RENDEZVOUS (APIC_IPI_INTS + 10) /* Inter-CPU rendezvous. */
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#define IPI_STOP (APIC_IPI_INTS + 11) /* Stop CPU until restarted. */
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#define APIC_SPURIOUS_INT 255
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#define LVT_LINT0 0
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#define LVT_LINT1 1
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#define LVT_TIMER 2
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#define LVT_ERROR 3
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#define LVT_PMC 4
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#define LVT_THERMAL 5
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#define LVT_MAX LVT_THERMAL
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#ifndef LOCORE
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#define APIC_IPI_DEST_SELF -1
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#define APIC_IPI_DEST_ALL -2
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#define APIC_IPI_DEST_OTHERS -3
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/*
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* An APIC enumerator is a psuedo bus driver that enumerates APIC's including
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* CPU's and I/O APIC's.
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*/
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struct apic_enumerator {
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const char *apic_name;
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int (*apic_probe)(void);
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int (*apic_probe_cpus)(void);
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int (*apic_setup_local)(void);
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int (*apic_setup_io)(void);
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SLIST_ENTRY(apic_enumerator) apic_next;
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};
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inthand_t
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IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3),
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IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6),
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IDTVEC(apic_isr7), IDTVEC(spuriousint);
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u_int apic_irq_to_idt(u_int irq);
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u_int apic_idt_to_irq(u_int vector);
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void apic_register_enumerator(struct apic_enumerator *enumerator);
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void *ioapic_create(uintptr_t addr, int32_t id, int intbase);
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int ioapic_disable_pin(void *cookie, u_int pin);
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void ioapic_enable_mixed_mode(void);
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int ioapic_get_vector(void *cookie, u_int pin);
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int ioapic_next_logical_cluster(void);
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void ioapic_register(void *cookie);
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int ioapic_remap_vector(void *cookie, u_int pin, int vector);
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int ioapic_set_extint(void *cookie, u_int pin);
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int ioapic_set_nmi(void *cookie, u_int pin);
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int ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol);
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int ioapic_set_triggermode(void *cookie, u_int pin,
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enum intr_trigger trigger);
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int ioapic_set_smi(void *cookie, u_int pin);
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void lapic_create(u_int apic_id, int boot_cpu);
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void lapic_disable(void);
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void lapic_dump(const char *str);
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void lapic_enable_intr(u_int vector);
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void lapic_eoi(void);
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int lapic_id(void);
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void lapic_init(uintptr_t addr);
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int lapic_intr_pending(u_int vector);
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void lapic_ipi_raw(register_t icrlo, u_int dest);
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void lapic_ipi_vectored(u_int vector, int dest);
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int lapic_ipi_wait(int delay);
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void lapic_handle_intr(struct intrframe frame);
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void lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id);
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int lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked);
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int lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode);
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int lapic_set_lvt_polarity(u_int apic_id, u_int lvt,
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enum intr_polarity pol);
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int lapic_set_lvt_triggermode(u_int apic_id, u_int lvt,
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enum intr_trigger trigger);
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void lapic_setup(void);
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#endif /* !LOCORE */
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#endif /* _MACHINE_APICVAR_H_ */
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