394 lines
10 KiB
C
394 lines
10 KiB
C
/*-
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* Device probe and attach routines for the following
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* Advanced Systems Inc. SCSI controllers:
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*
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* ABP[3]940UW - Bus-Master PCI Ultra-Wide (253 CDB)
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* ABP950UW - Dual Channel Bus-Master PCI Ultra-Wide (253 CDB/Channel)
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* ABP970UW - Bus-Master PCI Ultra-Wide (253 CDB)
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* ABP3940U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB)
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* ABP3950U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB)
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*
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* Copyright (c) 1998, 1999, 2000 Justin Gibbs.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <cam/cam.h>
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#include <cam/scsi/scsi_all.h>
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#include <dev/advansys/adwvar.h>
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#include <dev/advansys/adwlib.h>
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#include <dev/advansys/adwmcode.h>
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#define ADW_PCI_IOBASE PCIR_BAR(0) /* I/O Address */
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#define ADW_PCI_MEMBASE PCIR_BAR(1) /* Mem I/O Address */
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#define PCI_ID_ADVANSYS_3550 0x230010CD00000000ull
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#define PCI_ID_ADVANSYS_38C0800_REV1 0x250010CD00000000ull
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#define PCI_ID_ADVANSYS_38C1600_REV1 0x270010CD00000000ull
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#define PCI_ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
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#define PCI_ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
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struct adw_pci_identity;
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typedef int (adw_device_setup_t)(device_t, struct adw_pci_identity *,
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struct adw_softc *adw);
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struct adw_pci_identity {
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u_int64_t full_id;
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u_int64_t id_mask;
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char *name;
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adw_device_setup_t *setup;
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const struct adw_mcode *mcode_data;
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const struct adw_eeprom *default_eeprom;
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};
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static adw_device_setup_t adw_asc3550_setup;
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static adw_device_setup_t adw_asc38C0800_setup;
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#ifdef NOTYET
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static adw_device_setup_t adw_asc38C1600_setup;
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#endif
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struct adw_pci_identity adw_pci_ident_table[] =
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{
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/* asc3550 based controllers */
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{
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PCI_ID_ADVANSYS_3550,
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PCI_ID_DEV_VENDOR_MASK,
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"AdvanSys 3550 Ultra SCSI Adapter",
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adw_asc3550_setup,
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&adw_asc3550_mcode_data,
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&adw_asc3550_default_eeprom
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},
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/* asc38C0800 based controllers */
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{
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PCI_ID_ADVANSYS_38C0800_REV1,
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PCI_ID_DEV_VENDOR_MASK,
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"AdvanSys 38C0800 Ultra2 SCSI Adapter",
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adw_asc38C0800_setup,
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&adw_asc38C0800_mcode_data,
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&adw_asc38C0800_default_eeprom
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},
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#ifdef NOTYET
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/* XXX Disabled until I have hardware to test with */
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/* asc38C1600 based controllers */
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{
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PCI_ID_ADVANSYS_38C1600_REV1,
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PCI_ID_DEV_VENDOR_MASK,
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"AdvanSys 38C1600 Ultra160 SCSI Adapter",
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adw_asc38C1600_setup,
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NULL, /* None provided by vendor thus far */
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NULL /* None provided by vendor thus far */
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}
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#endif
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};
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#define ADW_PCI_MAX_DMA_ADDR (0xFFFFFFFFUL)
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#define ADW_PCI_MAX_DMA_COUNT (0xFFFFFFFFUL)
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static int adw_pci_probe(device_t dev);
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static int adw_pci_attach(device_t dev);
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static device_method_t adw_pci_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, adw_pci_probe),
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DEVMETHOD(device_attach, adw_pci_attach),
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{ 0, 0 }
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};
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static driver_t adw_pci_driver = {
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"adw",
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adw_pci_methods,
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sizeof(struct adw_softc)
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};
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static devclass_t adw_devclass;
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DRIVER_MODULE(adw, pci, adw_pci_driver, adw_devclass, 0, 0);
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MODULE_DEPEND(adw, pci, 1, 1, 1);
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static __inline u_int64_t
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adw_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
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{
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u_int64_t id;
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id = subvendor
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| (subdevice << 16)
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| ((u_int64_t)vendor << 32)
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| ((u_int64_t)device << 48);
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return (id);
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}
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static struct adw_pci_identity *
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adw_find_pci_device(device_t dev)
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{
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u_int64_t full_id;
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struct adw_pci_identity *entry;
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u_int i;
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full_id = adw_compose_id(pci_get_device(dev),
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pci_get_vendor(dev),
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pci_get_subdevice(dev),
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pci_get_subvendor(dev));
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for (i = 0; i < nitems(adw_pci_ident_table); i++) {
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entry = &adw_pci_ident_table[i];
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if (entry->full_id == (full_id & entry->id_mask))
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return (entry);
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}
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return (NULL);
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}
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static int
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adw_pci_probe(device_t dev)
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{
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struct adw_pci_identity *entry;
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entry = adw_find_pci_device(dev);
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if (entry != NULL) {
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device_set_desc(dev, entry->name);
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return (BUS_PROBE_DEFAULT);
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}
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return (ENXIO);
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}
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static int
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adw_pci_attach(device_t dev)
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{
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struct adw_softc *adw;
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struct adw_pci_identity *entry;
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u_int16_t command;
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struct resource *regs;
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int regs_type;
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int regs_id;
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int error;
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int zero;
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entry = adw_find_pci_device(dev);
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if (entry == NULL)
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return (ENXIO);
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regs = NULL;
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regs_type = 0;
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regs_id = 0;
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#ifdef ADW_ALLOW_MEMIO
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regs_type = SYS_RES_MEMORY;
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regs_id = ADW_PCI_MEMBASE;
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regs = bus_alloc_resource_any(dev, regs_type, ®s_id, RF_ACTIVE);
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#endif
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if (regs == NULL) {
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regs_type = SYS_RES_IOPORT;
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regs_id = ADW_PCI_IOBASE;
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regs = bus_alloc_resource_any(dev, regs_type,
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®s_id, RF_ACTIVE);
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}
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if (regs == NULL) {
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device_printf(dev, "can't allocate register resources\n");
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return (ENOMEM);
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}
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adw = adw_alloc(dev, regs, regs_type, regs_id);
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if (adw == NULL)
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return(ENOMEM);
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/*
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* Now that we have access to our registers, just verify that
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* this really is an AdvanSys device.
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*/
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if (adw_find_signature(adw) == 0) {
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adw_free(adw);
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return (ENXIO);
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}
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adw_reset_chip(adw);
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error = entry->setup(dev, entry, adw);
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if (error != 0)
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return (error);
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/* Ensure busmastering is enabled */
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pci_enable_busmaster(dev);
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/* Allocate a dmatag for our transfer DMA maps */
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error = bus_dma_tag_create(
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/* parent */ bus_get_dma_tag(dev),
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/* alignment */ 1,
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/* boundary */ 0,
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/* lowaddr */ ADW_PCI_MAX_DMA_ADDR,
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/* highaddr */ BUS_SPACE_MAXADDR,
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/* filter */ NULL,
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/* filterarg */ NULL,
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/* maxsize */ BUS_SPACE_MAXSIZE_32BIT,
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/* nsegments */ ~0,
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/* maxsegsz */ ADW_PCI_MAX_DMA_COUNT,
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/* flags */ 0,
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/* lockfunc */ NULL,
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/* lockarg */ NULL,
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&adw->parent_dmat);
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adw->init_level++;
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if (error != 0) {
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device_printf(dev, "Could not allocate DMA tag - error %d\n",
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error);
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adw_free(adw);
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return (error);
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}
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adw->init_level++;
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error = adw_init(adw);
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if (error != 0) {
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adw_free(adw);
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return (error);
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}
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/*
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* If the PCI Configuration Command Register "Parity Error Response
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* Control" Bit was clear (0), then set the microcode variable
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* 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
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* to ignore DMA parity errors.
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*/
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command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/2);
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if ((command & PCIM_CMD_PERRESPEN) == 0)
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adw_lram_write_16(adw, ADW_MC_CONTROL_FLAG,
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adw_lram_read_16(adw, ADW_MC_CONTROL_FLAG)
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| ADW_MC_CONTROL_IGN_PERR);
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zero = 0;
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adw->irq_res_type = SYS_RES_IRQ;
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adw->irq = bus_alloc_resource_any(dev, adw->irq_res_type, &zero,
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RF_ACTIVE | RF_SHAREABLE);
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if (adw->irq == NULL) {
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adw_free(adw);
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return (ENOMEM);
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}
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error = adw_attach(adw);
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if (error != 0)
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adw_free(adw);
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return (error);
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}
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static int
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adw_generic_setup(device_t dev, struct adw_pci_identity *entry,
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struct adw_softc *adw)
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{
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adw->channel = pci_get_function(dev) == 1 ? 'B' : 'A';
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adw->chip = ADW_CHIP_NONE;
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adw->features = ADW_FENONE;
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adw->flags = ADW_FNONE;
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adw->mcode_data = entry->mcode_data;
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adw->default_eeprom = entry->default_eeprom;
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return (0);
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}
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static int
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adw_asc3550_setup(device_t dev, struct adw_pci_identity *entry,
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struct adw_softc *adw)
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{
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int error;
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error = adw_generic_setup(dev, entry, adw);
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if (error != 0)
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return (error);
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adw->chip = ADW_CHIP_ASC3550;
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adw->features = ADW_ASC3550_FE;
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adw->memsize = ADW_3550_MEMSIZE;
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/*
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* For ASC-3550, setting the START_CTL_EMFU [3:2] bits
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* sets a FIFO threshold of 128 bytes. This register is
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* only accessible to the host.
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*/
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adw_outb(adw, ADW_DMA_CFG0,
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ADW_DMA_CFG0_START_CTL_EM_FU|ADW_DMA_CFG0_READ_CMD_MRM);
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adw_outb(adw, ADW_MEM_CFG,
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adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_8KB);
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return (0);
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}
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static int
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adw_asc38C0800_setup(device_t dev, struct adw_pci_identity *entry,
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struct adw_softc *adw)
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{
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int error;
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error = adw_generic_setup(dev, entry, adw);
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if (error != 0)
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return (error);
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/*
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* For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and
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* START_CTL_TH [3:2] bits for the default FIFO threshold.
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*
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* Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
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*
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* For DMA Errata #4 set the BC_THRESH_ENB bit.
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*/
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adw_outb(adw, ADW_DMA_CFG0,
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ADW_DMA_CFG0_BC_THRESH_ENB|ADW_DMA_CFG0_FIFO_THRESH_80B
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|ADW_DMA_CFG0_START_CTL_TH|ADW_DMA_CFG0_READ_CMD_MRM);
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adw_outb(adw, ADW_MEM_CFG,
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adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_16KB);
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adw->chip = ADW_CHIP_ASC38C0800;
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adw->features = ADW_ASC38C0800_FE;
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adw->memsize = ADW_38C0800_MEMSIZE;
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return (error);
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}
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#ifdef NOTYET
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static int
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adw_asc38C1600_setup(device_t dev, struct adw_pci_identity *entry,
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struct adw_softc *adw)
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{
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int error;
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error = adw_generic_setup(dev, entry, adw);
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if (error != 0)
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return (error);
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adw->chip = ADW_CHIP_ASC38C1600;
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adw->features = ADW_ASC38C1600_FE;
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adw->memsize = ADW_38C1600_MEMSIZE;
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return (error);
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}
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#endif
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