521 lines
15 KiB
C
521 lines
15 KiB
C
/*-
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* Copyright (c) 2003
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* Fraunhofer Institute for Open Communication Systems (FhG Fokus).
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Author: Hartmut Brandt <harti@freebsd.org>
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*
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* $FreeBSD$
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*
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* Driver for IDT77252 (ABR) based cards like ProSum's.
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*/
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/* legal values are 0, 1, 2 and 8 */
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#define PATM_VPI_BITS 2
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#define PATM_CFG_VPI IDT_CFG_VP2
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/* receive status queue size */
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#define PATM_RSQ_SIZE 512
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#define PATM_CFQ_RSQ_SIZE IDT_CFG_RXQ512
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/* alignment for SQ memory */
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#define PATM_SQ_ALIGNMENT 8192
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#define PATM_PROATM_NAME_OFFSET 060
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#define PATM_PROATM_NAME "PROATM"
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#define PATM_PROATM_MAC_OFFSET 044
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#define PATM_IDT_MAC_OFFSET 0154
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/* maximum number of packets on UBR queue */
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#define PATM_DLFT_MAXQ 1000
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/* maximum number of packets on other queues. This should depend on the
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* traffic contract. */
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#define PATM_TX_IFQLEN 100
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/*
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* Maximum number of DMA maps we allocate. This is the minimum that can be
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* set larger via a sysctl.
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* Starting number of DMA maps.
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* Step for growing.
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*/
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#define PATM_CFG_TXMAPS_MAX 1024
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#define PATM_CFG_TXMAPS_INIT 128
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#define PATM_CFG_TXMAPS_STEP 128
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/* percents of TST slots to keep for non-CBR traffic */
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#define PATM_TST_RESERVE 2
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/*
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* Structure to hold TX DMA maps
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*/
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struct patm_txmap {
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SLIST_ENTRY(patm_txmap) link;
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bus_dmamap_t map;
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};
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/*
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* Receive buffers.
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*
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* We manage our own external mbufs for small receive buffers for two reasons:
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* the card may consume a rather large number of buffers. Mapping each buffer
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* would consume a lot of iospace on sparc64. Also the card allows us to set
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* a 32-bit handle for identification of the buffers. On a 64-bit system this
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* requires us to use a mapping between buffers and handles.
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*
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* For large buffers we use mbuf clusters directly. We track these by using
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* an array of pointers (lbufs) to special structs and a free list of these
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* structs.
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*
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* For AAL0 cell we use FBQ2 and make the 1 cell long.
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*/
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/*
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* Define the small buffer chunk so that we have at least 16 byte free
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* at the end of the chunk and that there is an integral number of chunks
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* in a page.
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*/
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#define SMBUF_PAGE_SIZE 16384 /* 16k pages */
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#define SMBUF_MAX_PAGES 64 /* maximum number of pages */
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#define SMBUF_CHUNK_SIZE 256 /* 256 bytes per chunk */
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#define SMBUF_CELLS 5
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#define SMBUF_SIZE (SMBUF_CELLS * 48)
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#define SMBUF_THRESHOLD 9 /* 9/16 of queue size */
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#define SMBUF_NI_THRESH 3
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#define SMBUF_CI_THRESH 1
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#define VMBUF_PAGE_SIZE 16384 /* 16k pages */
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#define VMBUF_MAX_PAGES 16 /* maximum number of pages */
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#define VMBUF_CHUNK_SIZE 64 /* 64 bytes per chunk */
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#define VMBUF_CELLS 1
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#define VMBUF_SIZE (VMBUF_CELLS * 48)
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#define VMBUF_THRESHOLD 15 /* 15/16 of size */
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#define SMBUF_OFFSET (SMBUF_CHUNK_SIZE - 8 - SMBUF_SIZE)
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#define VMBUF_OFFSET 0
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#define MBUF_SHANDLE 0x00000000
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#define MBUF_LHANDLE 0x80000000
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#define MBUF_VHANDLE 0x40000000
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#define MBUF_HMASK 0x3fffffff
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/*
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* Large buffers
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*
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* The problem with these is the maximum count. When the card assembles
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* a AAL5 pdu it moves a buffer from the FBQ to the VC. This frees space
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* in the FBQ, put the buffer may pend on the card for an unlimited amount
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* of time (we don't idle connections). This means that the upper limit
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* on buffers on the card may be (no-of-open-vcs + FBQ_SIZE). Because
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* this is far too much, make this a tuneable. We could also make
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* this dynamic by allocating pages of several lbufs at once during run time.
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*/
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#define LMBUF_MAX (IDT_FBQ_SIZE * 2)
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#define LMBUF_CELLS (MCLBYTES / 48) /* 42 cells = 2048 byte */
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#define LMBUF_SIZE (LMBUF_CELLS * 48)
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#define LMBUF_THRESHOLD 9 /* 9/16 of queue size */
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#define LMBUF_OFFSET (MCLBYTES - LMBUF_SIZE)
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#define LMBUF_NI_THRESH 3
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#define LMBUF_CI_THRESH 1
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#define LMBUF_HANDLE 0x80000000
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struct lmbuf {
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SLIST_ENTRY(lmbuf) link; /* free list link */
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bus_dmamap_t map; /* DMA map */
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u_int handle; /* this is the handle index */
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struct mbuf *m; /* the current mbuf */
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bus_addr_t phy; /* phy addr */
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};
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#define PATM_CID(SC, VPI, VCI) \
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(((VPI) << IFP2IFATM((SC)->ifp)->mib.vci_bits) | (VCI))
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/*
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* Internal driver statistics
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*/
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struct patm_stats {
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uint32_t raw_cells;
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uint32_t raw_no_vcc;
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uint32_t raw_no_buf;
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uint32_t tx_qfull;
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uint32_t tx_out_of_tbds;
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uint32_t tx_out_of_maps;
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uint32_t tx_load_err;
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};
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/*
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* These are allocated as DMA able memory
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*/
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struct patm_scd {
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struct idt_tbd scq[IDT_SCQ_SIZE];
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LIST_ENTRY(patm_scd) link; /* all active SCDs */
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uint32_t sram; /* SRAM address */
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bus_addr_t phy; /* physical address */
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bus_dmamap_t map; /* DMA map */
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u_int tail; /* next free entry for host */
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int space; /* number of free entries (minus one) */
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u_int slots; /* CBR slots allocated */
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uint8_t tag; /* next tag for TSI */
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uint8_t last_tag; /* last tag checked in interrupt */
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uint8_t num_on_card; /* number of PDUs on tx queue */
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uint8_t lacr; /* LogACR value */
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uint8_t init_er; /* LogER value */
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struct ifqueue q; /* queue of packets */
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struct mbuf *on_card[IDT_TSQE_TAG_SPACE];
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};
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/*
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* Per-VCC data
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*/
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struct patm_vcc {
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struct atmio_vcc vcc; /* caller's parameters */
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void *rxhand; /* NATM handle */
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u_int vflags; /* open and other flags */
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uint32_t ipackets; /* packets received */
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uint32_t opackets; /* packets sent */
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uint64_t ibytes; /* bytes received */
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uint64_t obytes; /* bytes sent */
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struct mbuf *chain; /* currently received chain */
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struct mbuf *last; /* end of chain */
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u_int cid; /* index */
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u_int cps; /* last ABR cps */
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struct patm_scd *scd;
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};
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#define PATM_VCC_TX_OPEN 0x0001
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#define PATM_VCC_RX_OPEN 0x0002
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#define PATM_VCC_TX_CLOSING 0x0004
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#define PATM_VCC_RX_CLOSING 0x0008
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#define PATM_VCC_OPEN 0x000f /* all the above */
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#define PATM_RAW_CELL 0x0000 /* 53 byte cells */
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#define PATM_RAW_NOHEC 0x0100 /* 52 byte cells */
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#define PATM_RAW_CS 0x0200 /* 64 byte cell stream */
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#define PATM_RAW_FORMAT 0x0300 /* format mask */
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/*
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* Per adapter data
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*/
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struct patm_softc {
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struct ifnet *ifp; /* common ATM stuff */
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struct mtx mtx; /* lock */
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struct ifmedia media; /* media */
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device_t dev; /* device */
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struct resource * memres; /* memory resource */
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bus_space_handle_t memh; /* handle */
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bus_space_tag_t memt; /* ... and tag */
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int irqid; /* resource id */
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struct resource * irqres; /* resource */
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void * ih; /* interrupt handle */
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struct utopia utopia; /* phy state */
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const struct idt_mmap *mmap; /* SRAM memory map */
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u_int flags; /* see below */
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u_int revision; /* chip revision */
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/* DMAable status queue memory */
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size_t sq_size; /* size of memory area */
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bus_dma_tag_t sq_tag; /* DMA tag */
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bus_dmamap_t sq_map; /* map */
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bus_addr_t tsq_phy; /* phys addr. */
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struct idt_tsqe *tsq; /* transmit status queue */
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struct idt_tsqe *tsq_next; /* last processed entry */
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struct idt_rsqe *rsq; /* receive status queue */
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bus_addr_t rsq_phy; /* phys addr. */
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u_int rsq_last; /* last processed entry */
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struct idt_rawhnd *rawhnd; /* raw cell handle */
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bus_addr_t rawhnd_phy; /* phys addr. */
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/* TST */
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u_int tst_state; /* active TST and others */
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u_int tst_jump[2]; /* address of the jumps */
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u_int tst_base[2]; /* base address of TST */
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u_int *tst_soft; /* soft TST */
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struct mtx tst_lock;
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struct callout tst_callout;
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u_int tst_free; /* free slots */
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u_int tst_reserve; /* non-CBR reserve */
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u_int bwrem; /* remaining bandwidth */
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/* sysctl support */
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struct sysctl_ctx_list sysctl_ctx;
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struct sysctl_oid *sysctl_tree;
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/* EEPROM contents */
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uint8_t eeprom[256];
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/* large buffer mapping */
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bus_dma_tag_t lbuf_tag; /* DMA tag */
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u_int lbuf_max; /* maximum number */
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struct lmbuf *lbufs; /* array for indexing */
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SLIST_HEAD(,lmbuf) lbuf_free_list; /* free list */
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/* small buffer handling */
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bus_dma_tag_t sbuf_tag; /* DMA tag */
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struct mbpool *sbuf_pool; /* pool */
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struct mbpool *vbuf_pool; /* pool */
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/* raw cell queue */
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struct lmbuf *rawh; /* current header buf */
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u_int rawi; /* cell index into buffer */
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/* statistics */
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struct patm_stats stats; /* statistics */
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/* Vccs */
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struct patm_vcc **vccs; /* channel pointer array */
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u_int vccs_open; /* number of open channels */
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uma_zone_t vcc_zone;
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struct cv vcc_cv;
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/* SCDs */
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uint32_t scd_free; /* SRAM of first free SCD */
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bus_dma_tag_t scd_tag;
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struct patm_scd *scd0;
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LIST_HEAD(, patm_scd) scd_list; /* list of all active SCDs */
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/* Tx */
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bus_dma_tag_t tx_tag; /* for transmission */
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SLIST_HEAD(, patm_txmap) tx_maps_free; /* free maps */
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u_int tx_nmaps; /* allocated maps */
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u_int tx_maxmaps; /* maximum number */
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struct uma_zone *tx_mapzone; /* zone for maps */
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#ifdef PATM_DEBUG
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/* debugging */
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u_int debug;
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#endif
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};
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/* flags */
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#define PATM_25M 0x0001 /* 25MBit card */
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#define PATM_SBUFW 0x0002 /* warned */
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#define PATM_VBUFW 0x0004 /* warned */
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#define PATM_UNASS 0x0010 /* unassigned cells */
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#define PATM_CLR 0x0007 /* clear on stop */
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/* tst - uses unused fields */
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#define TST_BOTH 0x03000000
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#define TST_CH0 0x01000000
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#define TST_CH1 0x02000000
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/* tst_state */
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#define TST_ACT1 0x0001 /* active TST */
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#define TST_PENDING 0x0002 /* need update */
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#define TST_WAIT 0x0004 /* wait fo jump */
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#define patm_printf(SC, ...) if_printf((SC)->ifp, __VA_ARGS__);
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#ifdef PATM_DEBUG
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/*
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* Debugging
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*/
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enum {
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DBG_ATTACH = 0x0001, /* attaching the card */
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DBG_INTR = 0x0002, /* interrupts */
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DBG_REG = 0x0004, /* register access */
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DBG_SRAM = 0x0008, /* SRAM access */
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DBG_PHY = 0x0010, /* PHY access */
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DBG_IOCTL = 0x0020, /* ioctl */
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DBG_FREEQ = 0x0040, /* free bufq supply */
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DBG_VCC = 0x0080, /* open/close */
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DBG_TX = 0x0100, /* transmission */
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DBG_TST = 0x0200, /* TST */
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DBG_ALL = 0xffff
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};
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#define patm_debug(SC, FLAG, ...) do { \
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if((SC)->debug & DBG_##FLAG) { \
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if_printf((SC)->ifp, "%s: ", __func__); \
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printf(__VA_ARGS__); \
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printf("\n"); \
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} \
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} while (0)
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#else
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#define patm_debug(SC, FLAG, ...) do { } while (0)
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#endif
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/* start output */
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void patm_start(struct ifnet *);
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/* ioctl handler */
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int patm_ioctl(struct ifnet *, u_long, caddr_t);
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/* start the interface */
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void patm_init(void *);
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/* start the interface with the lock held */
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void patm_initialize(struct patm_softc *);
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/* stop the interface */
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void patm_stop(struct patm_softc *);
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/* software reset of interface */
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void patm_reset(struct patm_softc *);
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/* interrupt handler */
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void patm_intr(void *);
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/* check RSQ */
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void patm_intr_rsq(struct patm_softc *sc);
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/* enable the vcc */
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void patm_load_vc(struct patm_softc *sc, struct patm_vcc *vcc, int reload);
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/* close the given vcc for transmission */
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void patm_tx_vcc_close(struct patm_softc *, struct patm_vcc *);
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/* close the given vcc for receive */
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void patm_rx_vcc_close(struct patm_softc *, struct patm_vcc *);
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/* transmission side finally closed */
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void patm_tx_vcc_closed(struct patm_softc *, struct patm_vcc *);
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/* receive side finally closed */
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void patm_rx_vcc_closed(struct patm_softc *, struct patm_vcc *);
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/* vcc closed */
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void patm_vcc_closed(struct patm_softc *, struct patm_vcc *);
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/* check if we can open this one */
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int patm_tx_vcc_can_open(struct patm_softc *, struct patm_vcc *);
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/* check if we can open this one */
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int patm_rx_vcc_can_open(struct patm_softc *, struct patm_vcc *);
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/* open it */
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void patm_tx_vcc_open(struct patm_softc *, struct patm_vcc *);
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/* open it */
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void patm_rx_vcc_open(struct patm_softc *, struct patm_vcc *);
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/* receive packet */
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void patm_rx(struct patm_softc *, struct idt_rsqe *);
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/* packet transmitted */
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void patm_tx(struct patm_softc *, u_int, u_int);
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/* VBR connection went idle */
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void patm_tx_idle(struct patm_softc *, u_int);
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/* allocate an SCQ */
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struct patm_scd *patm_scd_alloc(struct patm_softc *);
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/* free an SCD */
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void patm_scd_free(struct patm_softc *sc, struct patm_scd *scd);
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/* setup SCD in SRAM */
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void patm_scd_setup(struct patm_softc *sc, struct patm_scd *scd);
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/* setup TCT entry in SRAM */
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void patm_tct_setup(struct patm_softc *, struct patm_scd *, struct patm_vcc *);
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/* free a large buffer */
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void patm_lbuf_free(struct patm_softc *sc, struct lmbuf *b);
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/* Process the raw cell at the given address */
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void patm_rx_raw(struct patm_softc *sc, u_char *cell);
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/* load a one segment DMA map */
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void patm_load_callback(void *, bus_dma_segment_t *, int, int);
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/* network operation register access */
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static __inline uint32_t
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patm_nor_read(struct patm_softc *sc, u_int reg)
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{
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uint32_t val;
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val = bus_space_read_4(sc->memt, sc->memh, reg);
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patm_debug(sc, REG, "reg(0x%x)=%04x", reg, val);
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return (val);
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}
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static __inline void
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patm_nor_write(struct patm_softc *sc, u_int reg, uint32_t val)
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{
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patm_debug(sc, REG, "reg(0x%x)=%04x", reg, val);
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bus_space_write_4(sc->memt, sc->memh, reg, val);
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}
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/* Execute command */
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static __inline void
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patm_cmd_wait(struct patm_softc *sc)
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{
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while (patm_nor_read(sc, IDT_NOR_STAT) & IDT_STAT_CMDBZ)
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;
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}
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static __inline void
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patm_cmd_exec(struct patm_softc *sc, uint32_t cmd)
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{
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patm_cmd_wait(sc);
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patm_nor_write(sc, IDT_NOR_CMD, cmd);
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}
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/* Read/write SRAM at the given word address. */
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static __inline uint32_t
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patm_sram_read(struct patm_softc *sc, u_int addr)
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{
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uint32_t val;
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patm_cmd_exec(sc, IDT_MKCMD_RSRAM(addr));
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patm_cmd_wait(sc);
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val = patm_nor_read(sc, IDT_NOR_D0);
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patm_debug(sc, SRAM, "read %04x=%08x", addr, val);
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return (val);
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}
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static __inline void
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patm_sram_write(struct patm_softc *sc, u_int addr, uint32_t val)
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{
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patm_debug(sc, SRAM, "write %04x=%08x", addr, val);
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patm_cmd_wait(sc);
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patm_nor_write(sc, IDT_NOR_D0, val);
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patm_cmd_exec(sc, IDT_MKCMD_WSRAM(addr, 0));
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}
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static __inline void
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patm_sram_write4(struct patm_softc *sc, u_int addr, uint32_t v0, uint32_t v1,
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uint32_t v2, uint32_t v3)
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{
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patm_debug(sc, SRAM, "write %04x=%08x,%08x,%08x,%08x",
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addr, v0, v1, v2, v3);
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patm_cmd_wait(sc);
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patm_nor_write(sc, IDT_NOR_D0, v0);
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patm_nor_write(sc, IDT_NOR_D1, v1);
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patm_nor_write(sc, IDT_NOR_D2, v2);
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patm_nor_write(sc, IDT_NOR_D3, v3);
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patm_cmd_exec(sc, IDT_MKCMD_WSRAM(addr, 3));
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}
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#define LEGAL_VPI(SC, VPI) \
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(((VPI) & ~((1 << IFP2IFATM((SC)->ifp)->mib.vpi_bits) - 1)) == 0)
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#define LEGAL_VCI(SC, VCI) \
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(((VCI) & ~((1 << IFP2IFATM((SC)->ifp)->mib.vci_bits) - 1)) == 0)
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extern const uint32_t patm_rtables155[];
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extern const uint32_t patm_rtables25[];
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extern const u_int patm_rtables_size;
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extern const u_int patm_rtables_ntab;
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