286 lines
9.0 KiB
C
286 lines
9.0 KiB
C
/*
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* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $Id: ar5212_keycache.c,v 1.4 2008/11/10 04:08:03 sam Exp $
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_internal.h"
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#include "ar5212/ar5212.h"
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#include "ar5212/ar5212reg.h"
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#include "ar5212/ar5212desc.h"
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/*
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* Note: The key cache hardware requires that each double-word
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* pair be written in even/odd order (since the destination is
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* a 64-bit register). Don't reorder the writes in this code
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* w/o considering this!
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*/
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#define KEY_XOR 0xaa
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#define IS_MIC_ENABLED(ah) \
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(AH5212(ah)->ah_staId1Defaults & AR_STA_ID1_CRPT_MIC_ENABLE)
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/*
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* Return the size of the hardware key cache.
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*/
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uint32_t
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ar5212GetKeyCacheSize(struct ath_hal *ah)
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{
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return AH_PRIVATE(ah)->ah_caps.halKeyCacheSize;
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}
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/*
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* Return true if the specific key cache entry is valid.
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*/
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HAL_BOOL
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ar5212IsKeyCacheEntryValid(struct ath_hal *ah, uint16_t entry)
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{
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if (entry < AH_PRIVATE(ah)->ah_caps.halKeyCacheSize) {
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uint32_t val = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry));
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if (val & AR_KEYTABLE_VALID)
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return AH_TRUE;
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}
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return AH_FALSE;
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}
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/*
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* Clear the specified key cache entry and any associated MIC entry.
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*/
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HAL_BOOL
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ar5212ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry)
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{
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uint32_t keyType;
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if (entry >= AH_PRIVATE(ah)->ah_caps.halKeyCacheSize) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n",
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__func__, entry);
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return AH_FALSE;
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}
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keyType = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry));
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/* XXX why not clear key type/valid bit first? */
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
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OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
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OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
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OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
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if (keyType == AR_KEYTABLE_TYPE_TKIP && IS_MIC_ENABLED(ah)) {
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uint16_t micentry = entry+64; /* MIC goes at slot+64 */
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HALASSERT(micentry < AH_PRIVATE(ah)->ah_caps.halKeyCacheSize);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
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/* NB: key type and MAC are known to be ok */
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}
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return AH_TRUE;
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}
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/*
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* Sets the mac part of the specified key cache entry (and any
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* associated MIC entry) and mark them valid.
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*/
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HAL_BOOL
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ar5212SetKeyCacheEntryMac(struct ath_hal *ah, uint16_t entry, const uint8_t *mac)
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{
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uint32_t macHi, macLo;
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if (entry >= AH_PRIVATE(ah)->ah_caps.halKeyCacheSize) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n",
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__func__, entry);
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return AH_FALSE;
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}
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/*
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* Set MAC address -- shifted right by 1. MacLo is
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* the 4 MSBs, and MacHi is the 2 LSBs.
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*/
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if (mac != AH_NULL) {
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macHi = (mac[5] << 8) | mac[4];
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macLo = (mac[3] << 24)| (mac[2] << 16)
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| (mac[1] << 8) | mac[0];
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macLo >>= 1;
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macLo |= (macHi & 1) << 31; /* carry */
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macHi >>= 1;
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} else {
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macLo = macHi = 0;
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}
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OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
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OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
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return AH_TRUE;
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}
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/*
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* Sets the contents of the specified key cache entry
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* and any associated MIC entry.
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*/
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HAL_BOOL
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ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,
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const HAL_KEYVAL *k, const uint8_t *mac,
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int xorKey)
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{
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struct ath_hal_5212 *ahp = AH5212(ah);
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const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
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uint32_t key0, key1, key2, key3, key4;
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uint32_t keyType;
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uint32_t xorMask = xorKey ?
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(KEY_XOR << 24 | KEY_XOR << 16 | KEY_XOR << 8 | KEY_XOR) : 0;
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if (entry >= pCap->halKeyCacheSize) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n",
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__func__, entry);
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return AH_FALSE;
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}
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switch (k->kv_type) {
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case HAL_CIPHER_AES_OCB:
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keyType = AR_KEYTABLE_TYPE_AES;
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break;
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case HAL_CIPHER_AES_CCM:
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if (!pCap->halCipherAesCcmSupport) {
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: AES-CCM not supported by mac rev 0x%x\n",
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__func__, AH_PRIVATE(ah)->ah_macRev);
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return AH_FALSE;
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}
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keyType = AR_KEYTABLE_TYPE_CCM;
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break;
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case HAL_CIPHER_TKIP:
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keyType = AR_KEYTABLE_TYPE_TKIP;
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if (IS_MIC_ENABLED(ah) && entry+64 >= pCap->halKeyCacheSize) {
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: entry %u inappropriate for TKIP\n",
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__func__, entry);
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return AH_FALSE;
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}
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break;
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case HAL_CIPHER_WEP:
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if (k->kv_len < 40 / NBBY) {
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: WEP key length %u too small\n",
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__func__, k->kv_len);
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return AH_FALSE;
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}
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if (k->kv_len <= 40 / NBBY)
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keyType = AR_KEYTABLE_TYPE_40;
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else if (k->kv_len <= 104 / NBBY)
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keyType = AR_KEYTABLE_TYPE_104;
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else
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keyType = AR_KEYTABLE_TYPE_128;
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break;
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case HAL_CIPHER_CLR:
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keyType = AR_KEYTABLE_TYPE_CLR;
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break;
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default:
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cipher %u not supported\n",
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__func__, k->kv_type);
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return AH_FALSE;
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}
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key0 = LE_READ_4(k->kv_val+0) ^ xorMask;
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key1 = (LE_READ_2(k->kv_val+4) ^ xorMask) & 0xffff;
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key2 = LE_READ_4(k->kv_val+6) ^ xorMask;
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key3 = (LE_READ_2(k->kv_val+10) ^ xorMask) & 0xffff;
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key4 = LE_READ_4(k->kv_val+12) ^ xorMask;
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if (k->kv_len <= 104 / NBBY)
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key4 &= 0xff;
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/*
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* Note: key cache hardware requires that each double-word
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* pair be written in even/odd order (since the destination is
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* a 64-bit register). Don't reorder these writes w/o
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* considering this!
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*/
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if (keyType == AR_KEYTABLE_TYPE_TKIP && IS_MIC_ENABLED(ah)) {
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uint16_t micentry = entry+64; /* MIC goes at slot+64 */
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uint32_t mic0, mic1, mic2, mic3, mic4;
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/*
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* Invalidate the encrypt/decrypt key until the MIC
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* key is installed so pending rx frames will fail
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* with decrypt errors rather than a MIC error.
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*/
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
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OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
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(void) ar5212SetKeyCacheEntryMac(ah, entry, mac);
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/*
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* Write MIC entry according to new or old key layout.
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* The MISC_MODE register is assumed already set so
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* these writes will be handled properly (happens on
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* attach and at every reset).
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*/
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/* RX mic */
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mic0 = LE_READ_4(k->kv_mic+0);
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mic2 = LE_READ_4(k->kv_mic+4);
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if (ahp->ah_miscMode & AR_MISC_MODE_MIC_NEW_LOC_ENABLE) {
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/*
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* Both RX and TX mic values can be combined into
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* one cache slot entry:
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* 8*N + 800 31:0 RX Michael key 0
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* 8*N + 804 15:0 TX Michael key 0 [31:16]
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* 8*N + 808 31:0 RX Michael key 1
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* 8*N + 80C 15:0 TX Michael key 0 [15:0]
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* 8*N + 810 31:0 TX Michael key 1
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* 8*N + 814 15:0 reserved
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* 8*N + 818 31:0 reserved
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* 8*N + 81C 14:0 reserved
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* 15 key valid == 0
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*/
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/* TX mic */
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mic1 = LE_READ_2(k->kv_txmic+2) & 0xffff;
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mic3 = LE_READ_2(k->kv_txmic+0) & 0xffff;
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mic4 = LE_READ_4(k->kv_txmic+4);
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} else {
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mic1 = mic3 = mic4 = 0;
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}
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
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OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
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AR_KEYTABLE_TYPE_CLR);
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/* NB: MIC key is not marked valid and has no MAC address */
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OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
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OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
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/* correct intentionally corrupted key */
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
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} else {
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
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OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
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(void) ar5212SetKeyCacheEntryMac(ah, entry, mac);
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}
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return AH_TRUE;
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}
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