179f14534e
This is an import of the reworked LEDE dts files. Besides other things they make it easier for us to reuse. The only diffs left are for the following SoCs: MT7620A (fbsd-mt7620a.dtsi) MT7621 (fbsd-mt7621.dtsi) MT7628 (fbsd-mt7628an.dtsi) RT3883 (fbsd-rt3883.dtsi) So we include the fbsd-*.dtsi files at the end of the original LEDE dtsi files, using '#include "fbsd-xxxx.dtsi"'. For example, for MT7621, the LEDE dtsi file is mt7621.dtsi. At the end of it we add: #include "fbsd-mt7621.dtsi" Approved by: adrian (mentor) Obtained from: LEDE project Sponsored by: Smartcom - Bulgaria AD Differential Revision: https://reviews.freebsd.org/D6394
479 lines
8.2 KiB
Plaintext
479 lines
8.2 KiB
Plaintext
/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "ralink,mtk7628an-soc";
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cpus {
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cpu@0 {
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compatible = "mips,mips24KEc";
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};
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};
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chosen {
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bootargs = "console=ttyS0,57600";
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};
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aliases {
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serial0 = &uartlite;
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};
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cpuintc: cpuintc@0 {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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palmbus: palmbus@10000000 {
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compatible = "palmbus";
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reg = <0x10000000 0x200000>;
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ranges = <0x0 0x10000000 0x1FFFFF>;
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#address-cells = <1>;
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#size-cells = <1>;
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sysc: sysc@0 {
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compatible = "ralink,mt7620a-sysc";
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reg = <0x0 0x100>;
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};
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watchdog: watchdog@120 {
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compatible = "ralink,mt7628an-wdt", "mtk,mt7621-wdt";
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reg = <0x120 0x10>;
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resets = <&rstctrl 8>;
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reset-names = "wdt";
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interrupt-parent = <&intc>;
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interrupts = <24>;
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};
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intc: intc@200 {
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compatible = "ralink,mt7628an-intc", "ralink,rt2880-intc";
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reg = <0x200 0x100>;
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resets = <&rstctrl 9>;
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reset-names = "intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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ralink,intc-registers = <0x9c 0xa0
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0x6c 0xa4
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0x80 0x78>;
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};
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memc: memc@300 {
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compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
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reg = <0x300 0x100>;
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resets = <&rstctrl 20>;
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reset-names = "mc";
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interrupt-parent = <&intc>;
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interrupts = <3>;
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};
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gpio@600 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
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reg = <0x600 0x100>;
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interrupt-parent = <&intc>;
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interrupts = <6>;
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gpio0: bank@0 {
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reg = <0>;
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compatible = "mtk,mt7621-gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio1: bank@1 {
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reg = <1>;
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compatible = "mtk,mt7621-gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio2: bank@2 {
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reg = <2>;
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compatible = "mtk,mt7621-gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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i2c: i2c@900 {
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compatible = "mediatek,mt7628-i2c";
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reg = <0x900 0x100>;
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resets = <&rstctrl 16>;
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reset-names = "i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c_pins>;
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};
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i2s: i2s@a00 {
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compatible = "ralink,mt7620a-i2s";
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reg = <0xa00 0x100>;
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resets = <&rstctrl 17>;
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reset-names = "i2s";
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interrupt-parent = <&intc>;
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interrupts = <10>;
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dmas = <&gdma 2>,
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<&gdma 3>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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spi0: spi@b00 {
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compatible = "ralink,mt7621-spi";
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reg = <0xb00 0x100>;
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resets = <&rstctrl 18>;
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reset-names = "spi";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi_pins>;
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status = "disabled";
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};
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uartlite: uartlite@c00 {
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compatible = "ns16550a";
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reg = <0xc00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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no-loopback-test;
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clock-frequency = <40000000>;
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resets = <&rstctrl 12>;
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reset-names = "uartl";
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interrupt-parent = <&intc>;
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interrupts = <20>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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};
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uart1: uart1@d00 {
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compatible = "ns16550a";
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reg = <0xd00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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no-loopback-test;
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clock-frequency = <40000000>;
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resets = <&rstctrl 19>;
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reset-names = "uart1";
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interrupt-parent = <&intc>;
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interrupts = <21>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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status = "disabled";
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};
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uart2: uart2@e00 {
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compatible = "ns16550a";
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reg = <0xe00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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no-loopback-test;
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clock-frequency = <40000000>;
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resets = <&rstctrl 20>;
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reset-names = "uart2";
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interrupt-parent = <&intc>;
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interrupts = <22>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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status = "disabled";
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};
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pwm: pwm@5000 {
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compatible = "mediatek,mt7628-pwm";
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reg = <0x5000 0x1000>;
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resets = <&rstctrl 31>;
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reset-names = "pwm";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>;
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status = "disabled";
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};
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pcm: pcm@2000 {
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compatible = "ralink,mt7620a-pcm";
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reg = <0x2000 0x800>;
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resets = <&rstctrl 11>;
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reset-names = "pcm";
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interrupt-parent = <&intc>;
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interrupts = <4>;
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status = "disabled";
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};
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gdma: gdma@2800 {
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compatible = "ralink,mt7620a-gdma", "ralink,rt2880-gdma";
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reg = <0x2800 0x800>;
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resets = <&rstctrl 14>;
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reset-names = "dma";
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interrupt-parent = <&intc>;
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interrupts = <7>;
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#dma-cells = <1>;
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#dma-channels = <16>;
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#dma-requests = <16>;
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status = "disabled";
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};
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};
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pinctrl: pinctrl {
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compatible = "ralink,rt2880-pinmux";
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinctrl0 {
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};
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spi_pins: spi {
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spi {
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ralink,group = "spi";
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ralink,function = "spi";
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};
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};
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spi_cs1_pins: spi_cs1 {
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spi_cs1 {
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ralink,group = "spi cs1";
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ralink,function = "spi cs1";
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};
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};
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i2c_pins: i2c {
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i2c {
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ralink,group = "i2c";
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ralink,function = "i2c";
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};
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};
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uart0_pins: uartlite {
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uartlite {
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ralink,group = "uart0";
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ralink,function = "uart0";
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};
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};
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uart1_pins: uart1 {
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uart1 {
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ralink,group = "uart1";
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ralink,function = "uart1";
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};
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};
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uart2_pins: uart2 {
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uart2 {
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ralink,group = "uart2";
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ralink,function = "uart2";
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};
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};
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sdxc_pins: sdxc {
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sdxc {
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ralink,group = "sdmode";
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ralink,function = "sdxc";
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};
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};
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pwm0_pins: pwm0 {
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pwm0 {
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ralink,group = "pwm0";
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ralink,function = "pwm0";
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};
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};
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pwm1_pins: pwm1 {
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pwm1 {
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ralink,group = "pwm1";
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ralink,function = "pwm1";
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};
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};
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pcm_i2s_pins: i2s {
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i2s {
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ralink,group = "i2s";
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ralink,function = "pcm";
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};
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};
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};
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rstctrl: rstctrl {
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compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
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#reset-cells = <1>;
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};
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clkctrl: clkctrl {
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compatible = "ralink,rt2880-clock";
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#clock-cells = <1>;
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};
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usbphy: usbphy@10120000 {
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compatible = "ralink,mt7628an-usbphy", "mediatek,mt7620-usbphy";
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reg = <0x10120000 0x4000>;
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#phy-cells = <1>;
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resets = <&rstctrl 22 &rstctrl 25>;
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reset-names = "host", "device";
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clocks = <&clkctrl 22 &clkctrl 25>;
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clock-names = "host", "device";
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};
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sdhci: sdhci@10130000 {
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compatible = "ralink,mt7620-sdhci";
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reg = <0x10130000 0x4000>;
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interrupt-parent = <&intc>;
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interrupts = <14>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdxc_pins>;
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status = "disabled";
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};
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ehci: ehci@101c0000 {
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compatible = "generic-ehci";
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reg = <0x101c0000 0x1000>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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interrupt-parent = <&intc>;
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interrupts = <18>;
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};
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ohci: ohci@101c1000 {
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compatible = "generic-ohci";
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reg = <0x101c1000 0x1000>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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interrupt-parent = <&intc>;
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interrupts = <18>;
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};
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ethernet: ethernet@10100000 {
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compatible = "ralink,rt5350-eth";
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reg = <0x10100000 0x10000>;
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interrupt-parent = <&cpuintc>;
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interrupts = <5>;
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resets = <&rstctrl 21 &rstctrl 23>;
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reset-names = "fe", "esw";
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mediatek,switch = <&esw>;
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};
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esw: esw@10110000 {
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compatible = "mediatek,mt7628-esw", "ralink,rt3050-esw";
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reg = <0x10110000 0x8000>;
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resets = <&rstctrl 23>;
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reset-names = "esw";
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interrupt-parent = <&intc>;
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interrupts = <17>;
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};
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pcie: pcie@10140000 {
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compatible = "mediatek,mt7620-pci";
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reg = <0x10140000 0x100
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0x10142000 0x100>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-parent = <&cpuintc>;
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interrupts = <4>;
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resets = <&rstctrl 26 &rstctrl 27>;
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reset-names = "pcie0", "pcie1";
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clocks = <&clkctrl 26 &clkctrl 27>;
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clock-names = "pcie0", "pcie1";
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status = "disabled";
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device_type = "pci";
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bus-range = <0 255>;
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ranges = <
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0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
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0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
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>;
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pcie-bridge {
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reg = <0x0000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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};
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};
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wmac: wmac@10300000 {
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compatible = "mediatek,mt7628-wmac";
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reg = <0x10300000 0x100000>;
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interrupt-parent = <&cpuintc>;
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interrupts = <6>;
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status = "disabled";
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mediatek,mtd-eeprom = <&factory 0x0000>;
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mediatek,5ghz = <0>;
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};
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};
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#include "fbsd-mt7628an.dtsi"
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