157 lines
3.9 KiB
C
157 lines
3.9 KiB
C
/*-
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* Copyright (c) 2011 Robert N. M. Watson
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MIPS_H_
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#define _MIPS_H_
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/*
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* 64-bit MIPS types.
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*/
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#if 0
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typedef unsigned long register_t; /* 64-bit MIPS register */
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#endif
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typedef unsigned long paddr_t; /* Physical address */
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typedef unsigned long vaddr_t; /* Virtual address */
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#if 0
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typedef unsigned char uint8_t;
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typedef unsigned short uint16_t;
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typedef unsigned int uint32_t;
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typedef unsigned long uint64_t;
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#endif
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/*
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* MIPS address space layout.
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*/
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#define MIPS_XKPHYS_UNCACHED_BASE 0x9000000000000000
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#define MIPS_XKPHYS_CACHED_NC_BASE 0x9800000000000000
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static inline vaddr_t
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mips_phys_to_cached(paddr_t phys)
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{
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return (phys | MIPS_XKPHYS_CACHED_NC_BASE);
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}
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static inline vaddr_t
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mips_phys_to_uncached(paddr_t phys)
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{
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return (phys | MIPS_XKPHYS_UNCACHED_BASE);
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}
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/*
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* Endian conversion routines for use in I/O -- most Altera devices are little
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* endian, but our processor is big endian.
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*/
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static inline uint16_t
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byteswap16(uint16_t v)
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{
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return ((v & 0xff00) >> 8 | (v & 0xff) << 8);
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}
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static inline uint32_t
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byteswap32(uint32_t v)
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{
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return ((v & 0xff000000) >> 24 | (v & 0x00ff0000) >> 8 |
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(v & 0x0000ff00) << 8 | (v & 0x000000ff) << 24);
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}
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/*
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* MIPS simple I/O routines -- arguments are virtual addresses so that the
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* caller can determine required caching properties.
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*/
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static inline uint8_t
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mips_ioread_uint8(vaddr_t vaddr)
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{
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uint8_t v;
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__asm__ __volatile__ ("lb %0, 0(%1)" : "=r" (v) : "r" (vaddr));
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return (v);
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}
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static inline void
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mips_iowrite_uint8(vaddr_t vaddr, uint8_t v)
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{
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__asm__ __volatile__ ("sb %0, 0(%1)" : : "r" (v), "r" (vaddr));
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}
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static inline uint32_t
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mips_ioread_uint32(vaddr_t vaddr)
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{
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uint32_t v;
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__asm__ __volatile__ ("lw %0, 0(%1)" : "=r" (v) : "r" (vaddr));
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return (v);
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}
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static inline void
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mips_iowrite_uint32(vaddr_t vaddr, uint32_t v)
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{
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__asm__ __volatile__ ("sw %0, 0(%1)" : : "r" (v), "r" (vaddr));
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}
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/*
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* Little-endian versions of 32-bit I/O routines.
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*/
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static inline uint32_t
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mips_ioread_uint32le(vaddr_t vaddr)
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{
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return (byteswap32(mips_ioread_uint32(vaddr)));
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}
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static inline void
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mips_iowrite_uint32le(vaddr_t vaddr, uint32_t v)
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{
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mips_iowrite_uint32(vaddr, byteswap32(v));
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}
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/*
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* Coprocessor 0 interfaces.
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*/
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static inline register_t
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cp0_count_get(void)
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{
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register_t count;
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__asm__ __volatile__ ("dmfc0 %0, $9" : "=r" (count));
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return (count);
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}
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#endif
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