430 lines
17 KiB
C
430 lines
17 KiB
C
/*-
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* Copyright (c) 2006 M. Warner Losh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* This software is derived from software provide by Kwikbyte who specifically
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* disclaimed copyright on the code.
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*
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* $FreeBSD$
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*/
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//*---------------------------------------------------------------------------
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//* ATMEL Microcontroller Software Support - ROUSSET -
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//*---------------------------------------------------------------------------
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//* The software is delivered "AS IS" without warranty or condition of any
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//* kind, either express, implied or statutory. This includes without
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//* limitation any warranty or condition with respect to merchantability or
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//* fitness for any particular purpose, or against the infringements of
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//* intellectual property rights of others.
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//*---------------------------------------------------------------------------
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//* File Name : AT91C_MCI_Device.h
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//* Object : Data Flash Atmel Description File
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//* Translator :
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//*
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//* 1.0 26/11/02 FB : Creation
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//*---------------------------------------------------------------------------
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#ifndef __MCI_Device_h
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#define __MCI_Device_h
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#include <sys/types.h>
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typedef unsigned int AT91S_MCIDeviceStatus;
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///////////////////////////////////////////////////////////////////////////////
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#define AT91C_CARD_REMOVED 0
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#define AT91C_MMC_CARD_INSERTED 1
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#define AT91C_SD_CARD_INSERTED 2
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#define AT91C_NO_ARGUMENT 0x0
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#define AT91C_FIRST_RCA 0xCAFE
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#define AT91C_MAX_MCI_CARDS 10
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#define AT91C_BUS_WIDTH_1BIT 0x00
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#define AT91C_BUS_WIDTH_4BITS 0x02
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/* Driver State */
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#define AT91C_MCI_IDLE 0x0
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#define AT91C_MCI_TIMEOUT_ERROR 0x1
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#define AT91C_MCI_RX_SINGLE_BLOCK 0x2
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#define AT91C_MCI_RX_MULTIPLE_BLOCK 0x3
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#define AT91C_MCI_RX_STREAM 0x4
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#define AT91C_MCI_TX_SINGLE_BLOCK 0x5
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#define AT91C_MCI_TX_MULTIPLE_BLOCK 0x6
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#define AT91C_MCI_TX_STREAM 0x7
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/* TimeOut */
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#define AT91C_TIMEOUT_CMDRDY 30
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///////////////////////////////////////////////////////////////////////////////
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// MMC & SDCard Structures
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///////////////////////////////////////////////////////////////////////////////
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/*---------------------------------------------*/
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/* MCI Device Structure Definition */
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/*---------------------------------------------*/
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typedef struct _AT91S_MciDevice
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{
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volatile unsigned char state;
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unsigned char SDCard_bus_width;
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unsigned int RCA; // RCA
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unsigned int READ_BL_LEN;
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#ifdef REPORT_SIZE
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unsigned int Memory_Capacity;
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#endif
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} AT91S_MciDevice;
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#include <dev/mmc/mmcreg.h>
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///////////////////////////////////////////////////////////////////////////////
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// Functions returnals
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///////////////////////////////////////////////////////////////////////////////
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#define AT91C_CMD_SEND_OK 0 // Command ok
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#define AT91C_CMD_SEND_ERROR -1 // Command failed
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#define AT91C_INIT_OK 2 // Init Successfull
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#define AT91C_INIT_ERROR 3 // Init Failed
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#define AT91C_READ_OK 4 // Read Successfull
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#define AT91C_READ_ERROR 5 // Read Failed
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#define AT91C_WRITE_OK 6 // Write Successfull
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#define AT91C_WRITE_ERROR 7 // Write Failed
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#define AT91C_ERASE_OK 8 // Erase Successfull
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#define AT91C_ERASE_ERROR 9 // Erase Failed
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#define AT91C_CARD_SELECTED_OK 10 // Card Selection Successfull
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#define AT91C_CARD_SELECTED_ERROR 11 // Card Selection Failed
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#define AT91C_MCI_SR_ERROR (AT91C_MCI_UNRE | AT91C_MCI_OVRE | AT91C_MCI_DTOE | \
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AT91C_MCI_DCRCE | AT91C_MCI_RTOE | AT91C_MCI_RENDE | AT91C_MCI_RCRCE | \
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AT91C_MCI_RDIRE | AT91C_MCI_RINDE)
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#define MMC_CMDNB (0x1Fu << 0) // Command Number
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#define MMC_RSPTYP (0x3u << 6) // Response Type
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#define MMC_RSPTYP_NO (0x0u << 6) // No response
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#define MMC_RSPTYP_48 (0x1u << 6) // 48-bit response
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#define MMC_RSPTYP_136 (0x2u << 6) // 136-bit response
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#define MMC_SPCMD (0x7u << 8) // Special CMD
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#define MMC_SPCMD_NONE (0x0u << 8) // Not a special CMD
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#define MMC_SPCMD_INIT (0x1u << 8) // Initialization CMD
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#define MMC_SPCMD_SYNC (0x2u << 8) // Synchronized CMD
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#define MMC_SPCMD_IT_CMD (0x4u << 8) // Interrupt command
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#define MMC_SPCMD_IT_REP (0x5u << 8) // Interrupt response
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#define MMC_OPDCMD (0x1u << 11) // Open Drain Command
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#define MMC_MAXLAT (0x1u << 12) // Maximum Latency for Command to respond
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#define MMC_TRCMD (0x3u << 16) // Transfer CMD
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#define MMC_TRCMD_NO (0x0u << 16) // No transfer
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#define MMC_TRCMD_START (0x1u << 16) // Start transfer
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#define MMC_TRCMD_STOP (0x2u << 16) // Stop transfer
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#define MMC_TRDIR (0x1u << 18) // Transfer Direction
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#define MMC_TRTYP (0x3u << 19) // Transfer Type
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#define MMC_TRTYP_BLOCK (0x0u << 19) // Block Transfer type
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#define MMC_TRTYP_MULTIPLE (0x1u << 19) // Multiple Block transfer type
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#define MMC_TRTYP_STREAM (0x2u << 19) // Stream transfer type
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///////////////////////////////////////////////////////////////////////////////
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// MCI_CMD Register Value
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///////////////////////////////////////////////////////////////////////////////
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#define POWER_ON_INIT \
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(0 | MMC_TRCMD_NO | MMC_SPCMD_INIT | MMC_OPDCMD)
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/////////////////////////////////////////////////////////////////
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// Class 0 & 1 commands: Basic commands and Read Stream commands
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/////////////////////////////////////////////////////////////////
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#define GO_IDLE_STATE_CMD \
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(0 | MMC_TRCMD_NO | MMC_SPCMD_NONE )
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#define MMC_GO_IDLE_STATE_CMD \
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(0 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_OPDCMD)
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#define MMC_SEND_OP_COND_CMD \
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(1 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \
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MMC_OPDCMD)
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#define ALL_SEND_CID_CMD \
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(2 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_136)
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#define MMC_ALL_SEND_CID_CMD \
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(2 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_136 | \
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MMC_OPDCMD)
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#define SET_RELATIVE_ADDR_CMD \
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(3 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \
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MMC_MAXLAT)
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#define MMC_SET_RELATIVE_ADDR_CMD \
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(3 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \
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MMC_MAXLAT | MMC_OPDCMD)
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#define SET_DSR_CMD \
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(4 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_NO | \
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MMC_MAXLAT) // no tested
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#define SEL_DESEL_CARD_CMD \
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(7 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \
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MMC_MAXLAT)
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#define SEND_CSD_CMD \
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(9 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_136 | \
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MMC_MAXLAT)
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#define SEND_CID_CMD \
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(10 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_136 | \
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MMC_MAXLAT)
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#define MMC_READ_DAT_UNTIL_STOP_CMD \
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(11 | MMC_TRTYP_STREAM | MMC_SPCMD_NONE | \
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MMC_RSPTYP_48 | MMC_TRDIR | MMC_TRCMD_START | \
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MMC_MAXLAT)
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#define STOP_TRANSMISSION_CMD \
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(12 | MMC_TRCMD_STOP | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \
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MMC_MAXLAT)
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#define STOP_TRANSMISSION_SYNC_CMD \
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(12 | MMC_TRCMD_STOP | MMC_SPCMD_SYNC | MMC_RSPTYP_48 | \
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MMC_MAXLAT)
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#define SEND_STATUS_CMD \
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(13 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \
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MMC_MAXLAT)
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#define GO_INACTIVE_STATE_CMD \
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(15 | MMC_RSPTYP_NO)
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//*------------------------------------------------
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//* Class 2 commands: Block oriented Read commands
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//*------------------------------------------------
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#define SET_BLOCKLEN_CMD (16 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_MAXLAT )
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#define READ_SINGLE_BLOCK_CMD (17 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_START | MMC_TRTYP_BLOCK | MMC_TRDIR | MMC_MAXLAT)
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#define READ_MULTIPLE_BLOCK_CMD (18 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_START | MMC_TRTYP_MULTIPLE | MMC_TRDIR | MMC_MAXLAT)
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//*--------------------------------------------
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//* Class 3 commands: Sequential write commands
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//*--------------------------------------------
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#define MMC_WRITE_DAT_UNTIL_STOP_CMD (20 | MMC_TRTYP_STREAM| MMC_SPCMD_NONE | MMC_RSPTYP_48 & ~(MMC_TRDIR) | MMC_TRCMD_START | MMC_MAXLAT ) // MMC
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//*------------------------------------------------
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//* Class 4 commands: Block oriented write commands
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//*------------------------------------------------
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#define WRITE_BLOCK_CMD (24 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_START | (MMC_TRTYP_BLOCK & ~(MMC_TRDIR)) | MMC_MAXLAT)
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#define WRITE_MULTIPLE_BLOCK_CMD (25 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_START | (MMC_TRTYP_MULTIPLE & ~(MMC_TRDIR)) | MMC_MAXLAT)
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#define PROGRAM_CSD_CMD (27 | MMC_RSPTYP_48 )
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//*----------------------------------------
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//* Class 6 commands: Group Write protect
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//*----------------------------------------
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#define SET_WRITE_PROT_CMD (28 | MMC_RSPTYP_48 )
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#define CLR_WRITE_PROT_CMD (29 | MMC_RSPTYP_48 )
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#define SEND_WRITE_PROT_CMD (30 | MMC_RSPTYP_48 )
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//*----------------------------------------
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//* Class 5 commands: Erase commands
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//*----------------------------------------
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#define TAG_SECTOR_START_CMD (32 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
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#define TAG_SECTOR_END_CMD (33 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
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#define MMC_UNTAG_SECTOR_CMD (34 | MMC_RSPTYP_48 )
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#define MMC_TAG_ERASE_GROUP_START_CMD (35 | MMC_RSPTYP_48 )
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#define MMC_TAG_ERASE_GROUP_END_CMD (36 | MMC_RSPTYP_48 )
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#define MMC_UNTAG_ERASE_GROUP_CMD (37 | MMC_RSPTYP_48 )
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#define ERASE_CMD (38 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT )
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//*----------------------------------------
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//* Class 7 commands: Lock commands
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//*----------------------------------------
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#define LOCK_UNLOCK (42 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) // no tested
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//*-----------------------------------------------
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// Class 8 commands: Application specific commands
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//*-----------------------------------------------
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#define APP_CMD (55 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
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#define GEN_CMD (56 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) // no tested
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#define SDCARD_SET_BUS_WIDTH_CMD (6 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
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#define SDCARD_STATUS_CMD (13 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
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#define SDCARD_SEND_NUM_WR_BLOCKS_CMD (22 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
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#define SDCARD_SET_WR_BLK_ERASE_COUNT_CMD (23 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
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#define SDCARD_APP_OP_COND_CMD (41 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO )
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#define SDCARD_SET_CLR_CARD_DETECT_CMD (42 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
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#define SDCARD_SEND_SCR_CMD (51 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
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#define SDCARD_APP_ALL_CMD (SDCARD_SET_BUS_WIDTH_CMD +\
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SDCARD_STATUS_CMD +\
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SDCARD_SEND_NUM_WR_BLOCKS_CMD +\
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SDCARD_SET_WR_BLK_ERASE_COUNT_CMD +\
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SDCARD_APP_OP_COND_CMD +\
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SDCARD_SET_CLR_CARD_DETECT_CMD +\
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SDCARD_SEND_SCR_CMD)
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//*----------------------------------------
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//* Class 9 commands: IO Mode commands
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//*----------------------------------------
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#define MMC_FAST_IO_CMD (39 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_MAXLAT)
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#define MMC_GO_IRQ_STATE_CMD (40 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
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///////////////////////////////////////////////////////////////////////////////
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// OCR Register
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///////////////////////////////////////////////////////////////////////////////
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#define AT91C_VDD_16_17 (1 << 4)
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#define AT91C_VDD_17_18 (1 << 5)
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#define AT91C_VDD_18_19 (1 << 6)
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#define AT91C_VDD_19_20 (1 << 7)
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#define AT91C_VDD_20_21 (1 << 8)
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#define AT91C_VDD_21_22 (1 << 9)
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#define AT91C_VDD_22_23 (1 << 10)
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#define AT91C_VDD_23_24 (1 << 11)
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#define AT91C_VDD_24_25 (1 << 12)
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#define AT91C_VDD_25_26 (1 << 13)
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#define AT91C_VDD_26_27 (1 << 14)
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#define AT91C_VDD_27_28 (1 << 15)
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#define AT91C_VDD_28_29 (1 << 16)
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#define AT91C_VDD_29_30 (1 << 17)
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#define AT91C_VDD_30_31 (1 << 18)
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#define AT91C_VDD_31_32 (1 << 19)
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#define AT91C_VDD_32_33 (1 << 20)
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#define AT91C_VDD_33_34 (1 << 21)
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#define AT91C_VDD_34_35 (1 << 22)
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#define AT91C_VDD_35_36 (1 << 23)
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#define AT91C_CARD_POWER_UP_BUSY (1 << 31)
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#define AT91C_MMC_HOST_VOLTAGE_RANGE (AT91C_VDD_27_28 | AT91C_VDD_28_29 | \
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AT91C_VDD_29_30 | AT91C_VDD_30_31 | AT91C_VDD_31_32 | AT91C_VDD_32_33)
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///////////////////////////////////////////////////////////////////////////////
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// CURRENT_STATE & READY_FOR_DATA in SDCard Status Register definition (response type R1)
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///////////////////////////////////////////////////////////////////////////////
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#define AT91C_SR_READY_FOR_DATA (1 << 8) // corresponds to buffer empty signalling on the bus
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#define AT91C_SR_IDLE (0 << 9)
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#define AT91C_SR_READY (1 << 9)
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#define AT91C_SR_IDENT (2 << 9)
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#define AT91C_SR_STBY (3 << 9)
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#define AT91C_SR_TRAN (4 << 9)
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#define AT91C_SR_DATA (5 << 9)
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#define AT91C_SR_RCV (6 << 9)
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#define AT91C_SR_PRG (7 << 9)
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#define AT91C_SR_DIS (8 << 9)
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#define AT91C_SR_CARD_SELECTED (AT91C_SR_READY_FOR_DATA + AT91C_SR_TRAN)
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#define MMC_FIRST_RCA 0xCAFE
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///////////////////////////////////////////////////////////////////////////////
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// MMC CSD register header File
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// CSD_x_xxx_S for shift value for word x
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// CSD_x_xxx_M for mask value for word x
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///////////////////////////////////////////////////////////////////////////////
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// First Response INT <=> CSD[3] : bits 0 to 31
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#define CSD_3_BIT0_S 0 // [0:0]
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#define CSD_3_BIT0_M 0x01
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#define CSD_3_CRC_S 1 // [7:1]
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#define CSD_3_CRC_M 0x7F
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#define CSD_3_MMC_ECC_S 8 // [9:8] reserved for MMC compatibility
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#define CSD_3_MMC_ECC_M 0x03
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#define CSD_3_FILE_FMT_S 10 // [11:10]
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#define CSD_3_FILE_FMT_M 0x03
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#define CSD_3_TMP_WP_S 12 // [12:12]
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#define CSD_3_TMP_WP_M 0x01
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#define CSD_3_PERM_WP_S 13 // [13:13]
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#define CSD_3_PERM_WP_M 0x01
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#define CSD_3_COPY_S 14 // [14:14]
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#define CSD_3_COPY_M 0x01
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#define CSD_3_FILE_FMT_GRP_S 15 // [15:15]
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#define CSD_3_FILE_FMT_GRP_M 0x01
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// reserved 16 // [20:16]
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// reserved 0x1F
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#define CSD_3_WBLOCK_P_S 21 // [21:21]
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#define CSD_3_WBLOCK_P_M 0x01
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#define CSD_3_WBLEN_S 22 // [25:22]
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#define CSD_3_WBLEN_M 0x0F
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#define CSD_3_R2W_F_S 26 // [28:26]
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#define CSD_3_R2W_F_M 0x07
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#define CSD_3_MMC_DEF_ECC_S 29 // [30:29] reserved for MMC compatibility
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#define CSD_3_MMC_DEF_ECC_M 0x03
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#define CSD_3_WP_GRP_EN_S 31 // [31:31]
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#define CSD_3_WP_GRP_EN_M 0x01
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// Seconde Response INT <=> CSD[2] : bits 32 to 63
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#define CSD_2_v21_WP_GRP_SIZE_S 0 // [38:32]
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#define CSD_2_v21_WP_GRP_SIZE_M 0x7F
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#define CSD_2_v21_SECT_SIZE_S 7 // [45:39]
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#define CSD_2_v21_SECT_SIZE_M 0x7F
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#define CSD_2_v21_ER_BLEN_EN_S 14 // [46:46]
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#define CSD_2_v21_ER_BLEN_EN_M 0x01
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#define CSD_2_v22_WP_GRP_SIZE_S 0 // [36:32]
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#define CSD_2_v22_WP_GRP_SIZE_M 0x1F
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#define CSD_2_v22_ER_GRP_SIZE_S 5 // [41:37]
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#define CSD_2_v22_ER_GRP_SIZE_M 0x1F
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#define CSD_2_v22_SECT_SIZE_S 10 // [46:42]
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#define CSD_2_v22_SECT_SIZE_M 0x1F
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#define CSD_2_C_SIZE_M_S 15 // [49:47]
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#define CSD_2_C_SIZE_M_M 0x07
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#define CSD_2_VDD_WMAX_S 18 // [52:50]
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#define CSD_2_VDD_WMAX_M 0x07
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#define CSD_2_VDD_WMIN_S 21 // [55:53]
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#define CSD_2_VDD_WMIN_M 0x07
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#define CSD_2_RCUR_MAX_S 24 // [58:56]
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#define CSD_2_RCUR_MAX_M 0x07
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#define CSD_2_RCUR_MIN_S 27 // [61:59]
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#define CSD_2_RCUR_MIN_M 0x07
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#define CSD_2_CSIZE_L_S 30 // [63:62] <=> 2 LSB of CSIZE
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#define CSD_2_CSIZE_L_M 0x03
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// Third Response INT <=> CSD[1] : bits 64 to 95
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#define CSD_1_CSIZE_H_S 0 // [73:64] <=> 10 MSB of CSIZE
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#define CSD_1_CSIZE_H_M 0x03FF
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// reserved 10 // [75:74]
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// reserved 0x03
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#define CSD_1_DSR_I_S 12 // [76:76]
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#define CSD_1_DSR_I_M 0x01
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#define CSD_1_RD_B_MIS_S 13 // [77:77]
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#define CSD_1_RD_B_MIS_M 0x01
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#define CSD_1_WR_B_MIS_S 14 // [78:78]
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#define CSD_1_WR_B_MIS_M 0x01
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#define CSD_1_RD_B_PAR_S 15 // [79:79]
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#define CSD_1_RD_B_PAR_M 0x01
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#define CSD_1_RD_B_LEN_S 16 // [83:80]
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#define CSD_1_RD_B_LEN_M 0x0F
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#define CSD_1_CCC_S 20 // [95:84]
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#define CSD_1_CCC_M 0x0FFF
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// Fourth Response INT <=> CSD[0] : bits 96 to 127
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#define CSD_0_TRANS_SPEED_S 0 // [103:96]
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#define CSD_0_TRANS_SPEED_M 0xFF
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#define CSD_0_NSAC_S 8 // [111:104]
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#define CSD_0_NSAC_M 0xFF
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#define CSD_0_TAAC_S 16 // [119:112]
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#define CSD_0_TAAC_M 0xFF
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// reserved 24 // [121:120]
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// reserved 0x03
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#define CSD_0_MMC_SPEC_VERS_S 26 // [125:122] reserved for MMC compatibility
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#define CSD_0_MMC_SPEC_VERS_M 0x0F
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#define CSD_0_STRUCT_S 30 // [127:126]
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#define CSD_0_STRUCT_M 0x03
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///////////////////////////////////////////////////////////////////////////////
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#endif
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