19d3b47b92
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
197 lines
5.3 KiB
C
197 lines
5.3 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
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* reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* NETLOGIC_BSD
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* $FreeBSD$
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*/
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#ifndef __NLM_HAL_CPUCONTROL_H__
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#define __NLM_HAL_CPUCONTROL_H__
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#define CPU_BLOCKID_IFU 0
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#define CPU_BLOCKID_ICU 1
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#define CPU_BLOCKID_IEU 2
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#define CPU_BLOCKID_LSU 3
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#define CPU_BLOCKID_MMU 4
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#define CPU_BLOCKID_PRF 5
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#define CPU_BLOCKID_SCH 7
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#define CPU_BLOCKID_SCU 8
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#define CPU_BLOCKID_FPU 9
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#define CPU_BLOCKID_MAP 10
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#define LSU_DEFEATURE 0x304
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#define LSU_DEBUG_ADDR 0x305
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#define LSU_DEBUG_DATA0 0x306
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#define LSU_CERRLOG_REGID 0x09
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#define SCHED_DEFEATURE 0x700
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/* Offsets of interest from the 'MAP' Block */
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#define MAP_THREADMODE 0x00
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#define MAP_EXT_EBASE_ENABLE 0x04
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#define MAP_CCDI_CONFIG 0x08
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#define MAP_THRD0_CCDI_STATUS 0x0c
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#define MAP_THRD1_CCDI_STATUS 0x10
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#define MAP_THRD2_CCDI_STATUS 0x14
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#define MAP_THRD3_CCDI_STATUS 0x18
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#define MAP_THRD0_DEBUG_MODE 0x1c
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#define MAP_THRD1_DEBUG_MODE 0x20
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#define MAP_THRD2_DEBUG_MODE 0x24
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#define MAP_THRD3_DEBUG_MODE 0x28
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#define MAP_MISC_STATE 0x60
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#define MAP_DEBUG_READ_CTL 0x64
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#define MAP_DEBUG_READ_REG0 0x68
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#define MAP_DEBUG_READ_REG1 0x6c
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#define MMU_SETUP 0x400
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#define MMU_LFSRSEED 0x401
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#define MMU_HPW_NUM_PAGE_LVL 0x410
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#define MMU_PGWKR_PGDBASE 0x411
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#define MMU_PGWKR_PGDSHFT 0x412
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#define MMU_PGWKR_PGDMASK 0x413
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#define MMU_PGWKR_PUDSHFT 0x414
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#define MMU_PGWKR_PUDMASK 0x415
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#define MMU_PGWKR_PMDSHFT 0x416
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#define MMU_PGWKR_PMDMASK 0x417
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#define MMU_PGWKR_PTESHFT 0x418
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#define MMU_PGWKR_PTEMASK 0x419
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#if !defined(LOCORE) && !defined(__ASSEMBLY__)
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#if defined(__mips_n64) || defined(__mips_n32)
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static __inline uint64_t
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nlm_mfcr(uint32_t reg)
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{
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uint64_t res;
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__asm__ __volatile__(
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".set push\n\t"
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".set noreorder\n\t"
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"move $9, %1\n\t"
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".word 0x71280018\n\t" /* mfcr $8, $9 */
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"move %0, $8\n\t"
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".set pop\n"
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: "=r" (res) : "r"(reg)
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: "$8", "$9"
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);
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return (res);
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}
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static __inline void
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nlm_mtcr(uint32_t reg, uint64_t value)
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{
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__asm__ __volatile__(
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".set push\n\t"
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".set noreorder\n\t"
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"move $8, %0\n"
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"move $9, %1\n"
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".word 0x71280019\n" /* mtcr $8, $9 */
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".set pop\n"
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:
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: "r" (value), "r" (reg)
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: "$8", "$9"
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);
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}
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#else /* !(defined(__mips_n64) || defined(__mips_n32)) */
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static __inline__ uint64_t
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nlm_mfcr(uint32_t reg)
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{
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uint32_t hi, lo;
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__asm__ __volatile__ (
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".set push\n"
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".set mips64\n"
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"move $8, %2\n"
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".word 0x71090018\n"
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"nop \n"
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"dsra32 %0, $9, 0\n"
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"sll %1, $9, 0\n"
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".set pop\n"
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: "=r"(hi), "=r"(lo)
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: "r"(reg) : "$8", "$9");
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return (((uint64_t)hi) << 32) | lo;
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}
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static __inline__ void
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nlm_mtcr(uint32_t reg, uint64_t val)
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{
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uint32_t hi, lo;
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hi = val >> 32;
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lo = val & 0xffffffff;
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__asm__ __volatile__ (
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".set push\n"
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".set mips64\n"
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"move $9, %0\n"
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"dsll32 $9, %1, 0\n"
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"dsll32 $8, %0, 0\n"
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"dsrl32 $9, $9, 0\n"
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"or $9, $9, $8\n"
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"move $8, %2\n"
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".word 0x71090019\n"
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"nop \n"
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".set pop\n"
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: :"r"(hi), "r"(lo), "r"(reg)
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: "$8", "$9");
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}
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#endif /* (defined(__mips_n64) || defined(__mips_n32)) */
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/* hashindex_en = 1 to enable hash mode, hashindex_en=0 to disable
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* global_mode = 1 to enable global mode, global_mode=0 to disable
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* clk_gating = 0 to enable clock gating, clk_gating=1 to disable
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*/
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static __inline__ void nlm_mmu_setup(int hashindex_en, int global_mode,
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int clk_gating)
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{
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uint32_t mmusetup = 0;
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mmusetup |= (hashindex_en << 13);
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mmusetup |= (clk_gating << 3);
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mmusetup |= (global_mode << 0);
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nlm_mtcr(MMU_SETUP, mmusetup);
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}
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static __inline__ void nlm_mmu_lfsr_seed (int thr0_seed, int thr1_seed,
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int thr2_seed, int thr3_seed)
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{
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uint32_t seed = nlm_mfcr(MMU_LFSRSEED);
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seed |= ((thr3_seed & 0x7f) << 23);
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seed |= ((thr2_seed & 0x7f) << 16);
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seed |= ((thr1_seed & 0x7f) << 7);
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seed |= ((thr0_seed & 0x7f) << 0);
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nlm_mtcr(MMU_LFSRSEED, seed);
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}
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#endif /* __ASSEMBLY__ */
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#endif /* __NLM_CPUCONTROL_H__ */
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