Landon J. Fuller b24852c2b3 Implement siba(4) support for bhnd_(read|write)_config. ... This provides access to the siba(4) bus-mapped per-core cfg0 register block. Approved by: adrian (mentor, implicit)		2016-08-27 00:58:21 +00:00
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bcma	bhnd(4): Include the chip model (e.g. BCM4xxx) in bhnd(4) bus's device	2016-08-27 00:07:48 +00:00
bhndb	bhnd(4): Initial PMU/PWRCTL power and clock management support.	2016-08-27 00:03:02 +00:00
cores	[mips/broadcom]: Replace static frequency table with generic PMU clock	2016-08-27 00:06:20 +00:00
nvram	bhnd(4): Initial PMU/PWRCTL power and clock management support.	2016-08-27 00:03:02 +00:00
siba	Implement siba(4) support for bhnd_(read|write)_config.	2016-08-27 00:58:21 +00:00
tools	bhnd(4): Implement NVRAM support required for PMU bring-up.	2016-08-16 21:32:05 +00:00
bhnd_bus_if.m	Implement siba(4) support for bhnd_(read|write)_config.	2016-08-27 00:58:21 +00:00
bhnd_core.h	bhnd(4): Initial PMU/PWRCTL power and clock management support.	2016-08-27 00:03:02 +00:00
bhnd_debug.h	[bhnd] Add logging macros to BHND.	2016-05-16 23:40:32 +00:00
bhnd_ids.h	bhnd(4): Initial PMU/PWRCTL power and clock management support.	2016-08-27 00:03:02 +00:00
bhnd_match.h	[bhnd] Normalize bhnd(4) device matching API	2016-05-24 21:20:17 +00:00
bhnd_nexus.c	bhnd(4): Fix resource allocation issues exposed by chipc PMU support.	2016-06-16 19:57:24 +00:00
bhnd_nexusvar.h	Switch mips/sentry5 to bhnd(4), and unify with mips/broadcom	2016-06-04 19:53:47 +00:00
bhnd_subr.c	bhnd(4): Include the chip model (e.g. BCM4xxx) in bhnd(4) bus's device	2016-08-27 00:07:48 +00:00
bhnd_types.h	bhnd(4): Initial PMU/PWRCTL power and clock management support.	2016-08-27 00:03:02 +00:00
bhnd.c	bhnd(4): Initial PMU/PWRCTL power and clock management support.	2016-08-27 00:03:02 +00:00
bhnd.h	bhnd(4): Include the chip model (e.g. BCM4xxx) in bhnd(4) bus's device	2016-08-27 00:07:48 +00:00
bhndreg.h
bhndvar.h	bhnd(4): Initial PMU/PWRCTL power and clock management support.	2016-08-27 00:03:02 +00:00