163 lines
5.4 KiB
C
163 lines
5.4 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2015 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _VGA_H_
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#define _VGA_H_
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#define VGA_IOPORT_START 0x3c0
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#define VGA_IOPORT_END 0x3df
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/* General registers */
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#define GEN_INPUT_STS0_PORT 0x3c2
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#define GEN_FEATURE_CTRL_PORT 0x3ca
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#define GEN_MISC_OUTPUT_PORT 0x3cc
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#define GEN_INPUT_STS1_MONO_PORT 0x3ba
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#define GEN_INPUT_STS1_COLOR_PORT 0x3da
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#define GEN_IS1_VR 0x08 /* Vertical retrace */
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#define GEN_IS1_DE 0x01 /* Display enable not */
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/* Attribute controller registers. */
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#define ATC_IDX_PORT 0x3c0
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#define ATC_DATA_PORT 0x3c1
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#define ATC_IDX_MASK 0x1f
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#define ATC_PALETTE0 0
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#define ATC_PALETTE15 15
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#define ATC_MODE_CONTROL 16
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#define ATC_MC_IPS 0x80 /* Internal palette size */
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#define ATC_MC_GA 0x01 /* Graphics/alphanumeric */
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#define ATC_OVERSCAN_COLOR 17
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#define ATC_COLOR_PLANE_ENABLE 18
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#define ATC_HORIZ_PIXEL_PANNING 19
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#define ATC_COLOR_SELECT 20
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#define ATC_CS_C67 0x0c /* Color select bits 6+7 */
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#define ATC_CS_C45 0x03 /* Color select bits 4+5 */
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/* Sequencer registers. */
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#define SEQ_IDX_PORT 0x3c4
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#define SEQ_DATA_PORT 0x3c5
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#define SEQ_RESET 0
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#define SEQ_RESET_ASYNC 0x1
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#define SEQ_RESET_SYNC 0x2
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#define SEQ_CLOCKING_MODE 1
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#define SEQ_CM_SO 0x20 /* Screen off */
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#define SEQ_CM_89 0x01 /* 8/9 dot clock */
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#define SEQ_MAP_MASK 2
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#define SEQ_CHAR_MAP_SELECT 3
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#define SEQ_CMS_SAH 0x20 /* Char map A bit 2 */
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#define SEQ_CMS_SAH_SHIFT 5
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#define SEQ_CMS_SA 0x0c /* Char map A bits 0+1 */
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#define SEQ_CMS_SA_SHIFT 2
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#define SEQ_CMS_SBH 0x10 /* Char map B bit 2 */
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#define SEQ_CMS_SBH_SHIFT 4
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#define SEQ_CMS_SB 0x03 /* Char map B bits 0+1 */
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#define SEQ_CMS_SB_SHIFT 0
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#define SEQ_MEMORY_MODE 4
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#define SEQ_MM_C4 0x08 /* Chain 4 */
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#define SEQ_MM_OE 0x04 /* Odd/even */
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#define SEQ_MM_EM 0x02 /* Extended memory */
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/* Graphics controller registers. */
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#define GC_IDX_PORT 0x3ce
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#define GC_DATA_PORT 0x3cf
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#define GC_SET_RESET 0
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#define GC_ENABLE_SET_RESET 1
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#define GC_COLOR_COMPARE 2
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#define GC_DATA_ROTATE 3
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#define GC_READ_MAP_SELECT 4
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#define GC_MODE 5
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#define GC_MODE_OE 0x10 /* Odd/even */
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#define GC_MODE_C4 0x04 /* Chain 4 */
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#define GC_MISCELLANEOUS 6
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#define GC_MISC_GM 0x01 /* Graphics/alphanumeric */
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#define GC_MISC_MM 0x0c /* memory map */
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#define GC_MISC_MM_SHIFT 2
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#define GC_COLOR_DONT_CARE 7
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#define GC_BIT_MASK 8
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/* CRT controller registers. */
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#define CRTC_IDX_MONO_PORT 0x3b4
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#define CRTC_DATA_MONO_PORT 0x3b5
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#define CRTC_IDX_COLOR_PORT 0x3d4
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#define CRTC_DATA_COLOR_PORT 0x3d5
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#define CRTC_HORIZ_TOTAL 0
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#define CRTC_HORIZ_DISP_END 1
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#define CRTC_START_HORIZ_BLANK 2
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#define CRTC_END_HORIZ_BLANK 3
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#define CRTC_START_HORIZ_RETRACE 4
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#define CRTC_END_HORIZ_RETRACE 5
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#define CRTC_VERT_TOTAL 6
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#define CRTC_OVERFLOW 7
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#define CRTC_OF_VRS9 0x80 /* VRS bit 9 */
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#define CRTC_OF_VRS9_SHIFT 7
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#define CRTC_OF_VDE9 0x40 /* VDE bit 9 */
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#define CRTC_OF_VDE9_SHIFT 6
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#define CRTC_OF_VRS8 0x04 /* VRS bit 8 */
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#define CRTC_OF_VRS8_SHIFT 2
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#define CRTC_OF_VDE8 0x02 /* VDE bit 8 */
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#define CRTC_OF_VDE8_SHIFT 1
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#define CRTC_PRESET_ROW_SCAN 8
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#define CRTC_MAX_SCAN_LINE 9
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#define CRTC_MSL_MSL 0x1f
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#define CRTC_CURSOR_START 10
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#define CRTC_CS_CO 0x20 /* Cursor off */
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#define CRTC_CS_CS 0x1f /* Cursor start */
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#define CRTC_CURSOR_END 11
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#define CRTC_CE_CE 0x1f /* Cursor end */
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#define CRTC_START_ADDR_HIGH 12
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#define CRTC_START_ADDR_LOW 13
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#define CRTC_CURSOR_LOC_HIGH 14
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#define CRTC_CURSOR_LOC_LOW 15
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#define CRTC_VERT_RETRACE_START 16
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#define CRTC_VERT_RETRACE_END 17
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#define CRTC_VRE_MASK 0xf
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#define CRTC_VERT_DISP_END 18
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#define CRTC_OFFSET 19
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#define CRTC_UNDERLINE_LOC 20
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#define CRTC_START_VERT_BLANK 21
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#define CRTC_END_VERT_BLANK 22
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#define CRTC_MODE_CONTROL 23
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#define CRTC_MC_TE 0x80 /* Timing enable */
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#define CRTC_LINE_COMPARE 24
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/* DAC registers */
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#define DAC_MASK 0x3c6
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#define DAC_IDX_RD_PORT 0x3c7
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#define DAC_IDX_WR_PORT 0x3c8
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#define DAC_DATA_PORT 0x3c9
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struct bhyvegc;
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void *vga_init(int io_only);
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void vga_render(struct bhyvegc *gc, void *arg);
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#endif /* _VGA_H_ */
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