27e2ad4687
This is a 2x2 2GHz 802.11n part. It works enough at the moment to bring up, scan and associate. I haven't started using this as a day to day AP. The specifics: * add honeybee initvals * add in changes; a mix from the QCA HAL and ath9k; * fix a bug in AR_SREV_AR9580_10_OR_LATER(), which is only used for one capability check and we don't even implement it - so it's a big no-op. Shady things: * ath9k has the "platform data" define the 25/40MHz clock. This HAL .. doesn't. Honeybee gets hard-coded to 25MHz which it likely shouldn't be. I'll have to go and identify/fix those. Tested: * Qualcomm Atheros AP143 reference design board. Obtained from: Qualcomm Atheros; Linux ath9k
343 lines
9.6 KiB
C
343 lines
9.6 KiB
C
/*
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* Copyright (c) 2013 Qualcomm Atheros, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
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* REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
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* INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
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* LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
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* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_desc.h"
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#include "ah_internal.h"
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#include "ar9300/ar9300.h"
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#include "ar9300/ar9300reg.h"
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#include "ar9300/ar9300desc.h"
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/*
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* Get the RXDP.
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*/
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u_int32_t
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ar9300_get_rx_dp(struct ath_hal *ath, HAL_RX_QUEUE qtype)
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{
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if (qtype == HAL_RX_QUEUE_HP) {
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return OS_REG_READ(ath, AR_HP_RXDP);
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} else {
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return OS_REG_READ(ath, AR_LP_RXDP);
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}
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}
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/*
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* Set the rx_dp.
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*/
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void
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ar9300_set_rx_dp(struct ath_hal *ah, u_int32_t rxdp, HAL_RX_QUEUE qtype)
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{
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HALASSERT((qtype == HAL_RX_QUEUE_HP) || (qtype == HAL_RX_QUEUE_LP));
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if (qtype == HAL_RX_QUEUE_HP) {
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OS_REG_WRITE(ah, AR_HP_RXDP, rxdp);
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} else {
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OS_REG_WRITE(ah, AR_LP_RXDP, rxdp);
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}
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}
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/*
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* Set Receive Enable bits.
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*/
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void
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ar9300_enable_receive(struct ath_hal *ah)
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{
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OS_REG_WRITE(ah, AR_CR, 0);
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}
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/*
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* Set the RX abort bit.
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*/
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HAL_BOOL
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ar9300_set_rx_abort(struct ath_hal *ah, HAL_BOOL set)
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{
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if (set) {
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/* Set the force_rx_abort bit */
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OS_REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
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if ( AH9300(ah)->ah_reset_reason == HAL_RESET_BBPANIC ){
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/* depending upon the BB panic status, rx state may not return to 0,
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* so skipping the wait for BB panic reset */
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OS_REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
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return AH_FALSE;
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} else {
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HAL_BOOL okay;
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okay = ath_hal_wait(
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ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, 0);
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/* Wait for Rx state to return to 0 */
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if (!okay) {
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/* abort: chip rx failed to go idle in 10 ms */
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OS_REG_CLR_BIT(ah, AR_DIAG_SW,
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(AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
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HALDEBUG(ah, HAL_DEBUG_RX,
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"%s: rx failed to go idle in 10 ms RXSM=0x%x\n",
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__func__, OS_REG_READ(ah, AR_OBS_BUS_1));
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return AH_FALSE; /* failure */
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}
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}
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} else {
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OS_REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
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}
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return AH_TRUE; /* success */
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}
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/*
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* Stop Receive at the DMA engine
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*/
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HAL_BOOL
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ar9300_stop_dma_receive(struct ath_hal *ah, u_int timeout)
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{
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int wait;
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HAL_BOOL status, okay;
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u_int32_t org_value;
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#define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
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#define AH_TIME_QUANTUM 100 /* usec */
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OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP);
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if (timeout == 0) {
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timeout = AH_RX_STOP_DMA_TIMEOUT;
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}
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org_value = OS_REG_READ(ah, AR_MACMISC);
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OS_REG_WRITE(ah, AR_MACMISC,
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((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
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(AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S)));
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okay = ath_hal_wait(
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ah, AR_DMADBG_7, AR_DMADBG_RX_STATE, 0);
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/* wait for Rx DMA state machine to become idle */
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if (!okay) {
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HALDEBUG(ah, HAL_DEBUG_RX,
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"reg AR_DMADBG_7 is not 0, instead 0x%08x\n",
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OS_REG_READ(ah, AR_DMADBG_7));
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}
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/* Set receive disable bit */
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OS_REG_WRITE(ah, AR_CR, AR_CR_RXD);
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/* Wait for rx enable bit to go low */
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for (wait = timeout / AH_TIME_QUANTUM; wait != 0; wait--) {
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if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) {
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break;
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}
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OS_DELAY(AH_TIME_QUANTUM);
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}
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if (wait == 0) {
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HALDEBUG(ah, HAL_DEBUG_RX, "%s: dma failed to stop in %d ms\n"
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"AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
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__func__,
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timeout / 1000,
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OS_REG_READ(ah, AR_CR),
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OS_REG_READ(ah, AR_DIAG_SW));
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status = AH_FALSE;
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} else {
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status = AH_TRUE;
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}
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OS_REG_WRITE(ah, AR_MACMISC, org_value);
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OS_MARK(ah, AH_MARK_RX_CTL,
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status ? AH_MARK_RX_CTL_DMA_STOP_OK : AH_MARK_RX_CTL_DMA_STOP_ERR);
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return status;
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#undef AH_RX_STOP_DMA_TIMEOUT
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#undef AH_TIME_QUANTUM
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}
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/*
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* Start Transmit at the PCU engine (unpause receive)
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*/
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void
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ar9300_start_pcu_receive(struct ath_hal *ah, HAL_BOOL is_scanning)
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{
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ar9300_enable_mib_counters(ah);
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ar9300_ani_reset(ah, is_scanning);
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/* Clear RX_DIS and RX_ABORT after enabling phy errors in ani_reset */
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OS_REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
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}
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/*
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* Stop Transmit at the PCU engine (pause receive)
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*/
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void
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ar9300_stop_pcu_receive(struct ath_hal *ah)
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{
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OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
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ar9300_disable_mib_counters(ah);
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}
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/*
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* Set multicast filter 0 (lower 32-bits)
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* filter 1 (upper 32-bits)
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*/
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void
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ar9300_set_multicast_filter(
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struct ath_hal *ah,
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u_int32_t filter0,
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u_int32_t filter1)
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{
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OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
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OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
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}
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/*
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* Get the receive filter.
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*/
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u_int32_t
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ar9300_get_rx_filter(struct ath_hal *ah)
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{
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u_int32_t bits = OS_REG_READ(ah, AR_RX_FILTER);
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u_int32_t phybits = OS_REG_READ(ah, AR_PHY_ERR);
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if (phybits & AR_PHY_ERR_RADAR) {
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bits |= HAL_RX_FILTER_PHYRADAR;
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}
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if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) {
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bits |= HAL_RX_FILTER_PHYERR;
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}
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return bits;
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}
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/*
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* Set the receive filter.
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*/
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void
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ar9300_set_rx_filter(struct ath_hal *ah, u_int32_t bits)
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{
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u_int32_t phybits;
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if (AR_SREV_SCORPION(ah) || AR_SREV_HONEYBEE(ah)) {
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/* Enable Rx for 4 address frames */
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bits |= AR_RX_4ADDRESS;
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}
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if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
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/* HW fix for rx hang and corruption. */
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bits |= AR_RX_CONTROL_WRAPPER;
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}
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OS_REG_WRITE(ah, AR_RX_FILTER,
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bits | AR_RX_UNCOM_BA_BAR | AR_RX_COMPR_BAR);
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phybits = 0;
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if (bits & HAL_RX_FILTER_PHYRADAR) {
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phybits |= AR_PHY_ERR_RADAR;
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}
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if (bits & HAL_RX_FILTER_PHYERR) {
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phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
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}
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OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
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if (phybits) {
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OS_REG_WRITE(ah, AR_RXCFG,
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OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
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} else {
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OS_REG_WRITE(ah, AR_RXCFG,
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OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
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}
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}
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/*
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* Select to pass PLCP headr or EVM data.
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*/
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HAL_BOOL
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ar9300_set_rx_sel_evm(struct ath_hal *ah, HAL_BOOL sel_evm, HAL_BOOL just_query)
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{
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struct ath_hal_9300 *ahp = AH9300(ah);
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HAL_BOOL old_value = ahp->ah_get_plcp_hdr == 0;
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if (just_query) {
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return old_value;
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}
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if (sel_evm) {
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OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_SEL_EVM);
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} else {
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OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_SEL_EVM);
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}
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ahp->ah_get_plcp_hdr = !sel_evm;
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return old_value;
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}
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void ar9300_promisc_mode(struct ath_hal *ah, HAL_BOOL enable)
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{
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u_int32_t reg_val = 0;
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reg_val = OS_REG_READ(ah, AR_RX_FILTER);
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if (enable){
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reg_val |= AR_RX_PROM;
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} else{ /*Disable promisc mode */
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reg_val &= ~AR_RX_PROM;
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}
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OS_REG_WRITE(ah, AR_RX_FILTER, reg_val);
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}
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void
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ar9300_read_pktlog_reg(
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struct ath_hal *ah,
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u_int32_t *rxfilter_val,
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u_int32_t *rxcfg_val,
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u_int32_t *phy_err_mask_val,
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u_int32_t *mac_pcu_phy_err_regval)
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{
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*rxfilter_val = OS_REG_READ(ah, AR_RX_FILTER);
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*rxcfg_val = OS_REG_READ(ah, AR_RXCFG);
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*phy_err_mask_val = OS_REG_READ(ah, AR_PHY_ERR);
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*mac_pcu_phy_err_regval = OS_REG_READ(ah, 0x8338);
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HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
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"%s[%d] rxfilter_val 0x%08x , rxcfg_val 0x%08x, "
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"phy_err_mask_val 0x%08x mac_pcu_phy_err_regval 0x%08x\n",
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__func__, __LINE__,
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*rxfilter_val, *rxcfg_val, *phy_err_mask_val, *mac_pcu_phy_err_regval);
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}
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void
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ar9300_write_pktlog_reg(
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struct ath_hal *ah,
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HAL_BOOL enable,
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u_int32_t rxfilter_val,
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u_int32_t rxcfg_val,
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u_int32_t phy_err_mask_val,
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u_int32_t mac_pcu_phy_err_reg_val)
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{
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if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
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/* HW fix for rx hang and corruption. */
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rxfilter_val |= AR_RX_CONTROL_WRAPPER;
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}
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if (enable) { /* Enable pktlog phyerr setting */
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OS_REG_WRITE(ah, AR_RX_FILTER, 0xffff | AR_RX_COMPR_BAR | rxfilter_val);
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OS_REG_WRITE(ah, AR_PHY_ERR, 0xFFFFFFFF);
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OS_REG_WRITE(ah, AR_RXCFG, rxcfg_val | AR_RXCFG_ZLFDMA);
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OS_REG_WRITE(ah, AR_PHY_ERR_MASK_REG, mac_pcu_phy_err_reg_val | 0xFF);
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} else { /* Disable phyerr and Restore regs */
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OS_REG_WRITE(ah, AR_RX_FILTER, rxfilter_val);
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OS_REG_WRITE(ah, AR_PHY_ERR, phy_err_mask_val);
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OS_REG_WRITE(ah, AR_RXCFG, rxcfg_val);
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OS_REG_WRITE(ah, AR_PHY_ERR_MASK_REG, mac_pcu_phy_err_reg_val);
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}
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HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
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"%s[%d] ena %d rxfilter_val 0x%08x , rxcfg_val 0x%08x, "
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"phy_err_mask_val 0x%08x mac_pcu_phy_err_regval 0x%08x\n",
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__func__, __LINE__,
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enable, rxfilter_val, rxcfg_val,
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phy_err_mask_val, mac_pcu_phy_err_reg_val);
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}
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