91 lines
3.3 KiB
C
91 lines
3.3 KiB
C
/*-
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* Copyright (c) 1998, 1999 Takanori Watanabe
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __INTPMREG_H__
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#define __INTPMREG_H__
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/* Register definitions for non-ICH Intel Chipset SMBUS controllers. */
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/* PCI Config Registers. */
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#define PCI_BASE_ADDR_SMB 0x90 /* IO BAR. */
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#define PCI_BASE_ADDR_PM 0x40
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#define PCI_HST_CFG_SMB 0xd2 /* Host Configuration */
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#define PCI_INTR_SMB_MASK 0xe
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#define PCI_INTR_SMB_SMI 0
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#define PCI_INTR_SMB_IRQ_PCI 2
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#define PCI_INTR_SMB_IRQ9 8
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#define PCI_INTR_SMB_ENABLE 1
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#define PCI_SLV_CMD_SMB 0xd3 /*SLAVE COMMAND*/
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#define PCI_SLV_SDW_SMB_1 0xd4 /*SLAVE SHADOW PORT 1*/
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#define PCI_SLV_SDW_SMB_2 0xd5 /*SLAVE SHADOW PORT 2*/
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#define PCI_REVID_SMB 0xd6
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/* PIXX4 SMBus Registers in the SMB BAR. */
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#define PIIX4_SMBHSTSTS 0x00
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#define PIIX4_SMBHSTSTAT_BUSY (1<<0)
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#define PIIX4_SMBHSTSTAT_INTR (1<<1)
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#define PIIX4_SMBHSTSTAT_ERR (1<<2)
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#define PIIX4_SMBHSTSTAT_BUSC (1<<3)
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#define PIIX4_SMBHSTSTAT_FAIL (1<<4)
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#define PIIX4_SMBSLVSTS 0x01
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#define PIIX4_SMBSLVSTS_ALART (1<<5)
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#define PIIX4_SMBSLVSTS_SDW2 (1<<4)
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#define PIIX4_SMBSLVSTS_SDW1 (1<<3)
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#define PIIX4_SMBSLVSTS_SLV (1<<2)
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#define PIIX4_SMBSLVSTS_BUSY (1<<0)
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#define PIIX4_SMBHSTCNT 0x02
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#define PIIX4_SMBHSTCNT_START (1<<6)
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#define PIIX4_SMBHSTCNT_PROT_QUICK 0
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#define PIIX4_SMBHSTCNT_PROT_BYTE (1<<2)
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#define PIIX4_SMBHSTCNT_PROT_BDATA (2<<2)
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#define PIIX4_SMBHSTCNT_PROT_WDATA (3<<2)
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#define PIIX4_SMBHSTCNT_PROT_BLOCK (5<<2)
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#define PIIX4_SMBHSTCNT_KILL (1<<1)
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#define PIIX4_SMBHSTCNT_INTREN (1)
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#define PIIX4_SMBHSTCMD 0x03
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#define PIIX4_SMBHSTADD 0x04
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#define LSB 0x1
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#define PIIX4_SMBHSTDAT0 0x05
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#define PIIX4_SMBHSTDAT1 0x06
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#define PIIX4_SMBBLKDAT 0x07
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#define PIIX4_SMBSLVCNT 0x08
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#define PIIX4_SMBSLVCNT_ALTEN (1<<3)
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#define PIIX4_SMBSLVCNT_SD2EN (1<<2)
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#define PIIX4_SMBSLVCNT_SD1EN (1<<1)
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#define PIIX4_SMBSLVCNT_SLVEN (1)
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#define PIIX4_SMBSLVCMD 0x09
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#define PIIX4_SMBSLVEVT 0x0a
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#define PIIX4_SMBSLVDAT 0x0c
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/* SMBus alert response address. */
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#define SMBALTRESP 0x18
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#define SMBBLOCKTRANS_MAX 32
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#endif /* !__INTPMREG_H__ */
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