219d14fe5f
Executive is a library that can be used by standalone applications and kernels to abstract access to Octeon SoC and board-specific hardware and facilities. The FreeBSD port to Octeon will be updated to use this where possible.
310 lines
11 KiB
C
310 lines
11 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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*
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
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* OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
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* RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
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* REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
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* DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
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* OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
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* PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
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* POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
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* OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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*
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*
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* For any questions regarding licensing please contact marketing@caviumnetworks.com
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*
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***********************license end**************************************/
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/**
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* @file
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*
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* Interface to the hardware Input Packet Data unit.
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*
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* <hr>$Revision: 41586 $<hr>
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*/
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#ifndef __CVMX_IPD_H__
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#define __CVMX_IPD_H__
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#ifndef CVMX_DONT_INCLUDE_CONFIG
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#include "executive-config.h"
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#ifdef CVMX_ENABLE_PKO_FUNCTIONS
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#include "cvmx-config.h"
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#endif
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef CVMX_ENABLE_LEN_M8_FIX
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#define CVMX_ENABLE_LEN_M8_FIX 0
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#endif
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/* CSR typedefs have been moved to cvmx-csr-*.h */
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typedef cvmx_ipd_mbuff_first_skip_t cvmx_ipd_mbuff_not_first_skip_t;
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typedef cvmx_ipd_first_next_ptr_back_t cvmx_ipd_second_next_ptr_back_t;
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/**
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* Configure IPD
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*
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* @param mbuff_size Packets buffer size in 8 byte words
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* @param first_mbuff_skip
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* Number of 8 byte words to skip in the first buffer
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* @param not_first_mbuff_skip
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* Number of 8 byte words to skip in each following buffer
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* @param first_back Must be same as first_mbuff_skip / 128
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* @param second_back
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* Must be same as not_first_mbuff_skip / 128
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* @param wqe_fpa_pool
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* FPA pool to get work entries from
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* @param cache_mode
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* @param back_pres_enable_flag
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* Enable or disable port back pressure
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*/
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static inline void cvmx_ipd_config(uint64_t mbuff_size,
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uint64_t first_mbuff_skip,
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uint64_t not_first_mbuff_skip,
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uint64_t first_back,
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uint64_t second_back,
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uint64_t wqe_fpa_pool,
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cvmx_ipd_mode_t cache_mode,
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uint64_t back_pres_enable_flag
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)
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{
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cvmx_ipd_mbuff_first_skip_t first_skip;
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cvmx_ipd_mbuff_not_first_skip_t not_first_skip;
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cvmx_ipd_mbuff_size_t size;
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cvmx_ipd_first_next_ptr_back_t first_back_struct;
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cvmx_ipd_second_next_ptr_back_t second_back_struct;
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cvmx_ipd_wqe_fpa_pool_t wqe_pool;
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cvmx_ipd_ctl_status_t ipd_ctl_reg;
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first_skip.u64 = 0;
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first_skip.s.skip_sz = first_mbuff_skip;
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cvmx_write_csr(CVMX_IPD_1ST_MBUFF_SKIP, first_skip.u64);
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not_first_skip.u64 = 0;
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not_first_skip.s.skip_sz = not_first_mbuff_skip;
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cvmx_write_csr(CVMX_IPD_NOT_1ST_MBUFF_SKIP, not_first_skip.u64);
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size.u64 = 0;
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size.s.mb_size = mbuff_size;
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cvmx_write_csr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64);
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first_back_struct.u64 = 0;
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first_back_struct.s.back = first_back;
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cvmx_write_csr(CVMX_IPD_1st_NEXT_PTR_BACK, first_back_struct.u64);
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second_back_struct.u64 = 0;
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second_back_struct.s.back = second_back;
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cvmx_write_csr(CVMX_IPD_2nd_NEXT_PTR_BACK,second_back_struct.u64);
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wqe_pool.u64 = 0;
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wqe_pool.s.wqe_pool = wqe_fpa_pool;
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cvmx_write_csr(CVMX_IPD_WQE_FPA_QUEUE, wqe_pool.u64);
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ipd_ctl_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
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ipd_ctl_reg.s.opc_mode = cache_mode;
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ipd_ctl_reg.s.pbp_en = back_pres_enable_flag;
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cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_reg.u64);
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/* Note: the example RED code that used to be here has been moved to
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cvmx_helper_setup_red */
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}
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/**
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* Enable IPD
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*/
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static inline void cvmx_ipd_enable(void)
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{
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cvmx_ipd_ctl_status_t ipd_reg;
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ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
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if (ipd_reg.s.ipd_en)
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{
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cvmx_dprintf("Warning: Enabling IPD when IPD already enabled.\n");
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}
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ipd_reg.s.ipd_en = TRUE;
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#if CVMX_ENABLE_LEN_M8_FIX
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if(!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
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ipd_reg.s.len_m8 = TRUE;
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}
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#endif
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cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
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}
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/**
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* Disable IPD
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*/
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static inline void cvmx_ipd_disable(void)
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{
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cvmx_ipd_ctl_status_t ipd_reg;
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ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
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ipd_reg.s.ipd_en = FALSE;
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cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
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}
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#ifdef CVMX_ENABLE_PKO_FUNCTIONS
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/**
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* Supportive function for cvmx_fpa_shutdown_pool.
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*/
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static inline void cvmx_ipd_free_ptr(void)
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{
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/* Only CN38XXp{1,2} cannot read pointer out of the IPD */
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if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1) && !OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
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int no_wptr = 0;
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cvmx_ipd_ptr_count_t ipd_ptr_count;
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ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT);
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/* Handle Work Queue Entry in cn56xx and cn52xx */
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if (octeon_has_feature(OCTEON_FEATURE_NO_WPTR)) {
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cvmx_ipd_ctl_status_t ipd_ctl_status;
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ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
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if (ipd_ctl_status.s.no_wptr)
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no_wptr = 1;
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}
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/* Free the prefetched WQE */
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if (ipd_ptr_count.s.wqev_cnt) {
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cvmx_ipd_wqe_ptr_valid_t ipd_wqe_ptr_valid;
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ipd_wqe_ptr_valid.u64 = cvmx_read_csr(CVMX_IPD_WQE_PTR_VALID);
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if (no_wptr)
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cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_wqe_ptr_valid.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
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else
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cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_wqe_ptr_valid.s.ptr<<7), CVMX_FPA_WQE_POOL, 0);
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}
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/* Free all WQE in the fifo */
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if (ipd_ptr_count.s.wqe_pcnt) {
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int i;
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cvmx_ipd_pwp_ptr_fifo_ctl_t ipd_pwp_ptr_fifo_ctl;
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ipd_pwp_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
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for (i = 0; i < ipd_ptr_count.s.wqe_pcnt; i++) {
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ipd_pwp_ptr_fifo_ctl.s.cena = 0;
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ipd_pwp_ptr_fifo_ctl.s.raddr = ipd_pwp_ptr_fifo_ctl.s.max_cnts + (ipd_pwp_ptr_fifo_ctl.s.wraddr+i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts;
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cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64);
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ipd_pwp_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
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if (no_wptr)
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cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_pwp_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
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else
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cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_pwp_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_WQE_POOL, 0);
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}
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ipd_pwp_ptr_fifo_ctl.s.cena = 1;
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cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64);
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}
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/* Free the prefetched packet */
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if (ipd_ptr_count.s.pktv_cnt) {
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cvmx_ipd_pkt_ptr_valid_t ipd_pkt_ptr_valid;
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ipd_pkt_ptr_valid.u64 = cvmx_read_csr(CVMX_IPD_PKT_PTR_VALID);
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cvmx_fpa_free(cvmx_phys_to_ptr(ipd_pkt_ptr_valid.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
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}
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/* Free the per port prefetched packets */
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if (1) {
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int i;
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cvmx_ipd_prc_port_ptr_fifo_ctl_t ipd_prc_port_ptr_fifo_ctl;
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ipd_prc_port_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL);
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for (i = 0; i < ipd_prc_port_ptr_fifo_ctl.s.max_pkt; i++) {
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ipd_prc_port_ptr_fifo_ctl.s.cena = 0;
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ipd_prc_port_ptr_fifo_ctl.s.raddr = i % ipd_prc_port_ptr_fifo_ctl.s.max_pkt;
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cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, ipd_prc_port_ptr_fifo_ctl.u64);
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ipd_prc_port_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL);
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cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_prc_port_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
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}
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ipd_prc_port_ptr_fifo_ctl.s.cena = 1;
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cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, ipd_prc_port_ptr_fifo_ctl.u64);
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}
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/* Free all packets in the holding fifo */
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if (ipd_ptr_count.s.pfif_cnt) {
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int i;
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cvmx_ipd_prc_hold_ptr_fifo_ctl_t ipd_prc_hold_ptr_fifo_ctl;
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ipd_prc_hold_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL);
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for (i = 0; i < ipd_ptr_count.s.pfif_cnt; i++) {
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ipd_prc_hold_ptr_fifo_ctl.s.cena = 0;
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ipd_prc_hold_ptr_fifo_ctl.s.raddr = (ipd_prc_hold_ptr_fifo_ctl.s.praddr + i) % ipd_prc_hold_ptr_fifo_ctl.s.max_pkt;
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cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, ipd_prc_hold_ptr_fifo_ctl.u64);
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ipd_prc_hold_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL);
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cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_prc_hold_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
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}
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ipd_prc_hold_ptr_fifo_ctl.s.cena = 1;
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cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, ipd_prc_hold_ptr_fifo_ctl.u64);
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}
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/* Free all packets in the fifo */
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if (ipd_ptr_count.s.pkt_pcnt) {
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int i;
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cvmx_ipd_pwp_ptr_fifo_ctl_t ipd_pwp_ptr_fifo_ctl;
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ipd_pwp_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
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for (i = 0; i < ipd_ptr_count.s.pkt_pcnt; i++) {
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ipd_pwp_ptr_fifo_ctl.s.cena = 0;
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ipd_pwp_ptr_fifo_ctl.s.raddr = (ipd_pwp_ptr_fifo_ctl.s.praddr+i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts;
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cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64);
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ipd_pwp_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
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cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_pwp_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
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}
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ipd_pwp_ptr_fifo_ctl.s.cena = 1;
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cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64);
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}
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/* Reset the IPD to get all buffers out of it */
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{
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cvmx_ipd_ctl_status_t ipd_ctl_status;
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ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
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ipd_ctl_status.s.reset = 1;
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cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64);
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}
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/* Reset the PIP */
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{
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cvmx_pip_sft_rst_t pip_sft_rst;
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pip_sft_rst.u64 = cvmx_read_csr(CVMX_PIP_SFT_RST);
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pip_sft_rst.s.rst = 1;
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cvmx_write_csr(CVMX_PIP_SFT_RST, pip_sft_rst.u64);
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}
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}
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}
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CVMX_IPD_H__ */
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