219d14fe5f
Executive is a library that can be used by standalone applications and kernels to abstract access to Octeon SoC and board-specific hardware and facilities. The FreeBSD port to Octeon will be updated to use this where possible.
521 lines
19 KiB
C
521 lines
19 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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*
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
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* OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
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* RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
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* REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
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* DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
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* OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
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* PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
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* POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
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* OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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*
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*
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* For any questions regarding licensing please contact marketing@caviumnetworks.com
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*
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***********************license end**************************************/
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/**
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* @file
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*
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* Support library for the SPI4000 card
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*
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* <hr>$Revision: 41586 $<hr>
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*/
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#include "cvmx.h"
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#include "cvmx-mio.h"
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#include "cvmx-spi.h"
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#include "cvmx-twsi.h"
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/* If someone is using an old config, make the SPI4000 act like RGMII for backpressure */
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#ifndef CVMX_HELPER_DISABLE_SPI4000_BACKPRESSURE
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#ifndef CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE
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#define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 0
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#endif
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#define CVMX_HELPER_DISABLE_SPI4000_BACKPRESSURE CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE
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#endif
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#define SPI4000_READ_ADDRESS_HIGH 0xf0
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#define SPI4000_READ_ADDRESS_LOW 0xf1
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#define SPI4000_WRITE_ADDRESS_HIGH 0xf2
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#define SPI4000_WRITE_ADDRESS_LOW 0xf3
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#define SPI4000_READ_DATA0 0xf4 /* High byte */
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#define SPI4000_READ_DATA1 0xf5
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#define SPI4000_READ_DATA2 0xf6
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#define SPI4000_READ_DATA3 0xf7 /* Low byte */
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#define SPI4000_WRITE_DATA0 0xf8 /* High byte */
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#define SPI4000_WRITE_DATA1 0xf9
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#define SPI4000_WRITE_DATA2 0xfa
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#define SPI4000_WRITE_DATA3 0xfb /* Low byte */
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#define SPI4000_DO_READ 0xfc /* Issue a read, returns read status */
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#define SPI4000_GET_READ_STATUS 0xfd /* 0xff: initial state, 2: Read failed, 1: Read pending, 0: Read success */
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#define SPI4000_DO_WRITE 0xfe /* Issue a write, returns write status */
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#define SPI4000_GET_WRITE_STATUS 0xff /* 0xff: initial state, 6: Write failed, 5: Write pending, 4: Write success */
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#define SPI4000_TWSI_ID(interface) (0x66 + interface)
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/* MDI Single Command (register 0x680) */
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typedef union
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{
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uint32_t u32;
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struct
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{
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uint32_t reserved_21_31 : 11;
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uint32_t mdi_command : 1; /**< Performs an MDIO access. When set, this bit
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self clears upon completion of the access. */
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uint32_t reserved_18_19 : 2;
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uint32_t op_code : 2; /**< MDIO Op Code
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00 = Reserved
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01 = Write Access
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10 = Read Access
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11 = Reserved */
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uint32_t reserved_13_15 : 3;
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uint32_t phy_address : 5; /**< Address of external PHY device */
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uint32_t reserved_5_7 : 3;
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uint32_t reg_address : 5; /**< Address of register within external PHY */
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} s;
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} mdio_single_command_t;
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static CVMX_SHARED int interface_is_spi4000[2] = {0,0};
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/**
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* @INTERNAL
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* Write data to the specified SPI4000 address
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*
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* @param interface Interface the SPI4000 is on. (0 or 1)
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* @param address Address to write to
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* @param data Data to write
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*/
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static void __cvmx_spi4000_write(int interface, int address, uint32_t data)
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{
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int status;
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cvmx_twsix_write_ia(0, SPI4000_TWSI_ID(interface), SPI4000_WRITE_ADDRESS_HIGH, 2, 1, address);
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cvmx_twsix_write_ia(0, SPI4000_TWSI_ID(interface), SPI4000_WRITE_DATA0, 4, 1, data);
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status = cvmx_twsi_read8(SPI4000_TWSI_ID(interface), SPI4000_DO_WRITE);
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while ((status == 5) || (status == 0xff))
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status = cvmx_twsi_read8(SPI4000_TWSI_ID(interface), SPI4000_GET_WRITE_STATUS);
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if (status != 4)
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cvmx_dprintf("SPI4000: write failed with status=0x%x\n", status);
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}
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/**
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* @INTERNAL
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* Read data from the SPI4000.
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*
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* @param interface Interface the SPI4000 is on. (0 or 1)
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* @param address Address to read from
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*
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* @return Value at the specified address
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*/
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static uint32_t __cvmx_spi4000_read(int interface, int address)
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{
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int status;
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uint64_t data;
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cvmx_twsix_write_ia(0, SPI4000_TWSI_ID(interface), SPI4000_READ_ADDRESS_HIGH, 2, 1, address);
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status = cvmx_twsi_read8(SPI4000_TWSI_ID(interface), SPI4000_DO_READ);
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while ((status == 1) || (status == 0xff))
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status = cvmx_twsi_read8(SPI4000_TWSI_ID(interface), SPI4000_GET_READ_STATUS);
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if (status)
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{
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cvmx_dprintf("SPI4000: read failed with %d\n", status);
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return 0;
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}
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status = cvmx_twsix_read_ia(0, SPI4000_TWSI_ID(interface), SPI4000_READ_DATA0, 4, 1, &data);
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if (status != 4)
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{
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cvmx_dprintf("SPI4000: read failed with %d\n", status);
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return 0;
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}
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return data;
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}
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/**
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* @INTERNAL
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* Write to a PHY using MDIO on the SPI4000
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*
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* @param interface Interface the SPI4000 is on. (0 or 1)
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* @param port SPI4000 RGMII port to write to. (0-9)
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* @param location MDIO register to write
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* @param val Value to write
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*/
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static void __cvmx_spi4000_mdio_write(int interface, int port, int location, int val)
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{
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static int last_value=-1;
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mdio_single_command_t mdio;
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mdio.u32 = 0;
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mdio.s.mdi_command = 1;
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mdio.s.op_code = 1;
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mdio.s.phy_address = port;
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mdio.s.reg_address = location;
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/* Since the TWSI accesses are very slow, don't update the write value
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if it is the same as the last value */
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if (val != last_value)
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{
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last_value = val;
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__cvmx_spi4000_write(interface, 0x0681, val);
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}
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__cvmx_spi4000_write(interface, 0x0680, mdio.u32);
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}
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/**
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* @INTERNAL
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* Read from a PHY using MDIO on the SPI4000
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*
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* @param interface Interface the SPI4000 is on. (0 or 1)
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* @param port SPI4000 RGMII port to read from. (0-9)
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* @param location MDIO register to read
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* @return The MDI read result
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*/
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static int __cvmx_spi4000_mdio_read(int interface, int port, int location)
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{
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mdio_single_command_t mdio;
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mdio.u32 = 0;
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mdio.s.mdi_command = 1;
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mdio.s.op_code = 2;
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mdio.s.phy_address = port;
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mdio.s.reg_address = location;
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__cvmx_spi4000_write(interface, 0x0680, mdio.u32);
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do
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{
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mdio.u32 = __cvmx_spi4000_read(interface, 0x0680);
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} while (mdio.s.mdi_command);
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return __cvmx_spi4000_read(interface, 0x0681) >> 16;
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}
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/**
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* @INTERNAL
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* Configure the SPI4000 MACs
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*/
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static void __cvmx_spi4000_configure_mac(int interface)
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{
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int port;
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// IXF1010 configuration
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// ---------------------
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//
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// Step 1: Apply soft reset to TxFIFO and MAC
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// MAC soft reset register. address=0x505
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// TxFIFO soft reset. address=0x620
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__cvmx_spi4000_write(interface, 0x0505, 0x3ff); // reset all the MACs
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__cvmx_spi4000_write(interface, 0x0620, 0x3ff); // reset the TX FIFOs
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// Global address and Configuration Register. address=0x500
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//
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// Step 2: Apply soft reset to RxFIFO and SPI.
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__cvmx_spi4000_write(interface, 0x059e, 0x3ff); // reset the RX FIFOs
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// Step 3a: Take the MAC out of softreset
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// MAC soft reset register. address=0x505
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__cvmx_spi4000_write(interface, 0x0505, 0x0); // reset all the MACs
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// Step 3b: De-assert port enables.
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// Global address and Configuration Register. address=0x500
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__cvmx_spi4000_write(interface, 0x0500, 0x0); // disable all ports
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// Step 4: Assert Clock mode change En.
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// Clock and interface mode Change En. address=Serdes base + 0x14
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// Serdes (Serializer/de-serializer). address=0x780
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// [Can't find this one]
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for (port=0; port < 10; port++)
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{
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int port_offset = port << 7;
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// Step 5: Set MAC interface mode GMII speed.
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// MAC interface mode and RGMII speed register.
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// address=port_index+0x10
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//
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// OUT port_index+0x10, 0x07 //RGMII 1000 Mbps operation.
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__cvmx_spi4000_write(interface, port_offset | 0x0010, 0x3);
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// Set the max packet size to 16383 bytes, including the CRC
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__cvmx_spi4000_write(interface, port_offset | 0x000f, 0x3fff);
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// Step 6: Change Interface to Copper mode
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// Interface mode register. address=0x501
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// [Can't find this]
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// Step 7: MAC configuration
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// Station address configuration.
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// Source MAC address low register. Source MAC address 31-0.
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// address=port_index+0x00
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// Source MAC address high register. Source MAC address 47-32.
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// address=port_index+0x01
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// where Port index is 0x0 to 0x5.
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// This address is inserted in the source address filed when
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// transmitting pause frames, and is also used to compare against
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// unicast pause frames at the receiving side.
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//
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// OUT port_index+0x00, source MAC address low.
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__cvmx_spi4000_write(interface, port_offset | 0x0000, 0x0000);
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// OUT port_index+0x01, source MAC address high.
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__cvmx_spi4000_write(interface, port_offset | 0x0001, 0x0000);
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// Step 8: Set desired duplex mode
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// Desired duplex register. address=port_index+0x02
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// [Reserved]
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// Step 9: Other configuration.
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// FC Enable Register. address=port_index+0x12
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// Discard Unknown Control Frame. address=port_index+0x15
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// Diverse config write register. address=port_index+0x18
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// RX Packet Filter register. address=port_index+0x19
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//
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// Step 9a: Tx FD FC Enabled / Rx FD FC Enabled
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if (CVMX_HELPER_DISABLE_SPI4000_BACKPRESSURE)
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__cvmx_spi4000_write(interface, port_offset | 0x0012, 0);
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else
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__cvmx_spi4000_write(interface, port_offset | 0x0012, 0x7);
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// Step 9b: Discard unknown control frames
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__cvmx_spi4000_write(interface, port_offset | 0x0015, 0x1);
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// Step 9c: Enable auto-CRC and auto-padding
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__cvmx_spi4000_write(interface, port_offset | 0x0018, 0x11cd); //??
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// Step 9d: Drop bad CRC / Drop Pause / No DAF
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__cvmx_spi4000_write(interface, port_offset | 0x0019, 0x00);
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}
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// Step 9d: Drop frames
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__cvmx_spi4000_write(interface, 0x059f, 0x03ff);
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for (port=0; port < 10; port++)
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{
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// Step 9e: Set the TX FIFO marks
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__cvmx_spi4000_write(interface, port + 0x0600, 0x0900); // TXFIFO High watermark
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__cvmx_spi4000_write(interface, port + 0x060a, 0x0800); // TXFIFO Low watermark
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__cvmx_spi4000_write(interface, port + 0x0614, 0x0380); // TXFIFO threshold
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}
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// Step 12: De-assert RxFIFO and SPI Rx/Tx reset
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__cvmx_spi4000_write(interface, 0x059e, 0x0); // reset the RX FIFOs
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// Step 13: De-assert TxFIFO and MAC reset
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__cvmx_spi4000_write(interface, 0x0620, 0x0); // reset the TX FIFOs
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// Step 14: Assert port enable
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// Global address and Configuration Register. address=0x500
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__cvmx_spi4000_write(interface, 0x0500, 0x03ff); // enable all ports
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// Step 15: Disable loopback
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// [Can't find this one]
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}
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/**
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* @INTERNAL
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* Configure the SPI4000 PHYs
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*/
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static void __cvmx_spi4000_configure_phy(int interface)
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{
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int port;
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/* We use separate loops below since it allows us to save a write
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to the SPI4000 for each repeated value. This adds up to a couple
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of seconds */
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/* Update the link state before resets. It takes a while for the links to
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come back after the resets. Most likely they'll come back the same as
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they are now */
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for (port=0; port < 10; port++)
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cvmx_spi4000_check_speed(interface, port);
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/* Enable RGMII DELAYS for TX_CLK and RX_CLK (see spec) */
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for (port=0; port < 10; port++)
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__cvmx_spi4000_mdio_write(interface, port, 0x14, 0x00e2);
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/* Advertise pause and 100 Full Duplex. Don't advertise half duplex or 10Mbpa */
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for (port=0; port < 10; port++)
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__cvmx_spi4000_mdio_write(interface, port, 0x4, 0x0d01);
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/* Enable PHY reset */
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for (port=0; port < 10; port++)
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__cvmx_spi4000_mdio_write(interface, port, 0x0, 0x9140);
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}
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/**
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* Poll all the SPI4000 port and check its speed
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*
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* @param interface Interface the SPI4000 is on
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* @param port Port to poll (0-9)
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* @return Status of the port. 0=down. All other values the port is up.
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*/
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cvmx_gmxx_rxx_rx_inbnd_t cvmx_spi4000_check_speed(int interface, int port)
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{
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static int phy_status[10] = {0,};
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cvmx_gmxx_rxx_rx_inbnd_t link;
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int read_status;
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link.u64 = 0;
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if (!interface_is_spi4000[interface])
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return link;
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if (port>=10)
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return link;
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/* Register 0x11: PHY Specific Status Register
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Register Function Setting Mode HW Rst SW Rst Notes
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RO 00 Retain note
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17.15:14 Speed 11 = Reserved
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17.a
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10 = 1000 Mbps
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01 = 100 Mbps
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00 = 10 Mbps
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17.13 Duplex 1 = Full-duplex RO 0 Retain note
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0 = Half-duplex 17.a
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17.12 Page Received 1 = Page received RO, LH 0 0
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0 = Page not received
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1 = Resolved RO 0 0 note
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17.11 Speed and
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0 = Not resolved 17.a
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Duplex
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Resolved
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17.10 Link (real time) 1 = Link up RO 0 0
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0 = Link down
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RO 000 000 note
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000 = < 50m
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17.9:7 Cable Length
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001 = 50 - 80m 17.b
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(100/1000
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010 = 80 - 110m
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modes only)
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011 = 110 - 140m
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100 = >140m
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17.6 MDI Crossover 1 = MDIX RO 0 0 note
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Status 0 = MDI 17.a
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17.5 Downshift Sta- 1 = Downshift RO 0 0
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tus 0 = No Downshift
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17.4 Energy Detect 1 = Sleep RO 0 0
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Status 0 = Active
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17.3 Transmit Pause 1 = Transmit pause enabled RO 0 0 note17.
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Enabled 0 = Transmit pause disabled a, 17.c
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17.2 Receive Pause 1 = Receive pause enabled RO 0 0 note17.
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Enabled 0 = Receive pause disabled a, 17.c
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17.1 Polarity (real 1 = Reversed RO 0 0
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time) 0 = Normal
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17.0 Jabber (real 1 = Jabber RO 0 Retain
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time) 0 = No jabber
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*/
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read_status = __cvmx_spi4000_mdio_read(interface, port, 0x11);
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if ((read_status & (1<<10)) == 0)
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read_status = 0; /* If the link is down, force zero */
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else
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read_status &= 0xe400; /* Strip off all the don't care bits */
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if (read_status != phy_status[port])
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{
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phy_status[port] = read_status;
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if (read_status & (1<<10))
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{
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/* If the link is up, we need to set the speed based on the PHY status */
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if (read_status & (1<<15))
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__cvmx_spi4000_write(interface, (port<<7) | 0x0010, 0x3); /* 1Gbps */
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else
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__cvmx_spi4000_write(interface, (port<<7) | 0x0010, 0x1); /* 100Mbps */
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}
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else
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{
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/* If the link is down, force 1Gbps so TX traffic dumps fast */
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__cvmx_spi4000_write(interface, (port<<7) | 0x0010, 0x3); /* 1Gbps */
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}
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}
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if (read_status & (1<<10))
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{
|
|
link.s.status = 1; /* Link up */
|
|
if (read_status & (1<<15))
|
|
link.s.speed = 2;
|
|
else
|
|
link.s.speed = 1;
|
|
}
|
|
else
|
|
{
|
|
link.s.speed = 2; /* Use 1Gbps when down */
|
|
link.s.status = 0; /* Link Down */
|
|
}
|
|
link.s.duplex = ((read_status & (1<<13)) != 0);
|
|
|
|
return link;
|
|
}
|
|
|
|
|
|
/**
|
|
* Return non-zero if the SPI interface has a SPI4000 attached
|
|
*
|
|
* @param interface SPI interface the SPI4000 is connected to
|
|
*
|
|
* @return
|
|
*/
|
|
int cvmx_spi4000_is_present(int interface)
|
|
{
|
|
if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
|
|
return 0;
|
|
// Check for the presence of a SPI4000. If it isn't there,
|
|
// these writes will timeout.
|
|
if (cvmx_twsi_write8(SPI4000_TWSI_ID(interface), SPI4000_WRITE_ADDRESS_HIGH, 0))
|
|
return 0;
|
|
if (cvmx_twsi_write8(SPI4000_TWSI_ID(interface), SPI4000_WRITE_ADDRESS_LOW, 0))
|
|
return 0;
|
|
interface_is_spi4000[interface] = 1;
|
|
return 1;
|
|
}
|
|
|
|
|
|
/**
|
|
* Initialize the SPI4000 for use
|
|
*
|
|
* @param interface SPI interface the SPI4000 is connected to
|
|
*/
|
|
int cvmx_spi4000_initialize(int interface)
|
|
{
|
|
if (!cvmx_spi4000_is_present(interface))
|
|
return -1;
|
|
|
|
__cvmx_spi4000_configure_mac(interface);
|
|
__cvmx_spi4000_configure_phy(interface);
|
|
return 0;
|
|
}
|
|
|