b92f01b79c
ones implemented using assembly. o) Use TRAPF_USERMODE() consistently rather than USERMODE(). Eliminate <machine/psl.h> as a result. o) Use intr_*() rather than *intr(), consistently. o) Use register_t instead of u_int in some trap code. o) Merge some more endian-related macros to machine/asm.h from NetBSD. o) Add PTR_LI macro, which loads an address with the correct sign-extension for a pointer. o) Restore interrupts when bailing out due to an excessive IRQ in nexus_setup_intr(). o) Remove unused functions from psraccess.S. o) Enter temporary virtual entries for large memory access into the page tables rather than simply hoping they stay resident in the TLB and we don't need to do a refill for them. o) Abstract out large memory mapping setup/teardown using some macros. o) Do mips_dcache_wbinv_range() when using temporary virtual addresses just like we do when we can use the direct map.
128 lines
4.4 KiB
C
128 lines
4.4 KiB
C
/* $OpenBSD: trap.h,v 1.3 1999/01/27 04:46:06 imp Exp $ */
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/*-
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* Copyright (c) 1988 University of Utah.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department and Ralph Campbell.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: Utah Hdr: trap.h 1.1 90/07/09
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* from: @(#)trap.h 8.1 (Berkeley) 6/10/93
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* JNPR: trap.h,v 1.3 2006/12/02 09:53:41 katta
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* $FreeBSD$
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*/
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#ifndef _MACHINE_TRAP_H_
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#define _MACHINE_TRAP_H_
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/*
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* Trap codes also known in trap.c for name strings.
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* Used for indexing so modify with care.
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*/
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#define T_INT 0 /* Interrupt pending */
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#define T_TLB_MOD 1 /* TLB modified fault */
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#define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */
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#define T_TLB_ST_MISS 3 /* TLB miss on a store */
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#define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */
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#define T_ADDR_ERR_ST 5 /* Address error on a store */
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#define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */
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#define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */
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#define T_SYSCALL 8 /* System call */
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#define T_BREAK 9 /* Breakpoint */
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#define T_RES_INST 10 /* Reserved instruction exception */
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#define T_COP_UNUSABLE 11 /* Coprocessor unusable */
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#define T_OVFLOW 12 /* Arithmetic overflow */
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#define T_TRAP 13 /* Trap instruction */
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#define T_VCEI 14 /* Virtual coherency instruction */
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#define T_FPE 15 /* Floating point exception */
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#define T_IWATCH 16 /* Inst. Watch address reference */
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#define T_C2E 18 /* Exception from coprocessor 2 */
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#define T_DWATCH 23 /* Data Watch address reference */
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#define T_MCHECK 24 /* Received an MCHECK */
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#define T_VCED 31 /* Virtual coherency data */
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#define T_USER 0x20 /* user-mode flag or'ed with type */
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#if !defined(SMP) && (defined(DDB) || defined(DEBUG))
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struct trapdebug { /* trap history buffer for debugging */
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register_t status;
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register_t cause;
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register_t vadr;
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register_t pc;
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register_t ra;
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register_t sp;
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register_t code;
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};
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#define trapdebug_enter(x, cd) { \
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register_t s = intr_disable(); \
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trp->status = x->sr; \
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trp->cause = x->cause; \
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trp->vadr = x->badvaddr; \
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trp->pc = x->pc; \
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trp->sp = x->sp; \
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trp->ra = x->ra; \
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trp->code = cd; \
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if (++trp == &trapdebug[TRAPSIZE]) \
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trp = trapdebug; \
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intr_restore(s); \
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}
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#define TRAPSIZE 10 /* Trap log buffer length */
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extern struct trapdebug trapdebug[TRAPSIZE], *trp;
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void trapDump(char *msg);
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#else
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#define trapdebug_enter(x, cd)
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#endif
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void MipsFPTrap(u_int, u_int, u_int);
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void MipsKernGenException(void);
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void MipsKernIntr(void);
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void MipsTLBInvalidException(void);
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void MipsTLBMissException(void);
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void MipsUserGenException(void);
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void MipsUserIntr(void);
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register_t trap(struct trapframe *);
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#ifndef LOCORE /* XXX */
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int check_address(void *);
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void platform_trap_enter(void);
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void platform_trap_exit(void);
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#endif
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#endif /* !_MACHINE_TRAP_H_ */
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