9844b3b3ab
These realtek switch PHYs speak a variant of i2c with some slightly modified handling. From the submitter, slightly modified now that some further digging has been done: The I2C framework makes a assumption that the read/not-write bit of the first byte (the address) indicates whether reads or writes are to follow. The RTL8366 family uses the bus: after sending the address+read/not-write byte, two register address bytes are sent, then the 16-bit register value is sent or received. While the register write access can be performed as a 4-byte write, the read access requires the read bit to be set, but the first two bytes for the register address then need to be transmitted. This patch maintains the i2c protocol behaviour but allows it to be relaxed (for these kinds of switch PHYs, and whatever else Realtek may do with this almost-but-not-quite i2c bus) - by setting the "strict" hint to 0. The "strict" hint defaults to 1. Submitted by: Stefan Bethke <stb@lassitu.de>
73 lines
2.4 KiB
C
73 lines
2.4 KiB
C
/*-
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* Copyright (c) 1998 Nicolas Souchu
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef __IICBUS_H
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#define __IICBUS_H
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#include <sys/_lock.h>
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#include <sys/_mutex.h>
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#define IICBUS_IVAR(d) (struct iicbus_ivar *) device_get_ivars(d)
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#define IICBUS_SOFTC(d) (struct iicbus_softc *) device_get_softc(d)
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struct iicbus_softc
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{
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device_t dev; /* Myself */
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device_t owner; /* iicbus owner device structure */
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u_char started; /* address of the 'started' slave
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* 0 if no start condition succeeded */
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u_char strict; /* deny operations that violate the
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* I2C protocol */
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struct mtx lock;
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};
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struct iicbus_ivar
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{
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uint32_t addr;
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};
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enum {
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IICBUS_IVAR_ADDR /* Address or base address */
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};
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#define IICBUS_ACCESSOR(A, B, T) \
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__BUS_ACCESSOR(iicbus, A, IICBUS, B, T)
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IICBUS_ACCESSOR(addr, ADDR, uint32_t)
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#define IICBUS_LOCK(sc) mtx_lock(&(sc)->lock)
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#define IICBUS_UNLOCK(sc) mtx_unlock(&(sc)->lock)
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#define IICBUS_ASSERT_LOCKED(sc) mtx_assert(&(sc)->lock, MA_OWNED)
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extern int iicbus_generic_intr(device_t dev, int event, char *buf);
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extern driver_t iicbus_driver;
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extern devclass_t iicbus_devclass;
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#endif
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