3df266dff9
The core clock (armclk) on RockChip SoC is special. It can derive it's clock from many PLLs but RockChip recommand to do it from "apll" on old SoC and "npll" on new SoC. The reason for choosing npll is that it's have less jitter and is more close to the arm core on the SoC. r333314 added the core clock as a composite clock but due to it's specials property we need to deal with it differently. A new rk_clk_armclk type is added for this and it supports only the "npll" as we don't run on old RockChip SoC that only have the "apll". It will always reparent to "npll" and set the frequency according to a rate table that is known to be good. For now we set the "npll" to the desired frequency and just set the core clk divider to 1 as its parent it just used for the core clk. |
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| acpica | ||
| arm64 | ||
| cavium | ||
| cloudabi32 | ||
| cloudabi64 | ||
| conf | ||
| coresight | ||
| include | ||
| linux | ||
| qualcomm | ||
| rockchip | ||