b3e9732a76
the legacy 8259A PICs. - Implement an ICH-comptabile PCI interrupt router on the lpc device with 8 steerable pins configured via config space access to byte-wide registers at 0x60-63 and 0x68-6b. - For each configured PCI INTx interrupt, route it to both an I/O APIC pin and a PCI interrupt router pin. When a PCI INTx interrupt is asserted, ensure that both pins are asserted. - Provide an initial routing of PCI interrupt router (PIRQ) pins to 8259A pins (ISA IRQs) and initialize the interrupt line config register for the corresponding PCI function with the ISA IRQ as this matches existing hardware. - Add a global _PIC method for OSPM to select the desired interrupt routing configuration. - Update the _PRT methods for PCI bridges to provide both APIC and legacy PRT tables and return the appropriate table based on the configured routing configuration. Note that if the lpc device is not configured, no routing information is provided. - When the lpc device is enabled, provide ACPI PCI link devices corresponding to each PIRQ pin. - Add a VMM ioctl to adjust the trigger mode (edge vs level) for 8259A pins via the ELCR. - Mark the power management SCI as level triggered. - Don't hardcode the number of elements in Packages in the source for the DSDT. iasl(8) will fill in the actual number of elements, and this makes it simpler to generate a Package with a variable number of elements. Reviewed by: tycho
350 lines
9.0 KiB
C
350 lines
9.0 KiB
C
/*-
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* Copyright (c) 2014 Advanced Computing Technologies LLC
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* Written by: John H. Baldwin <jhb@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <machine/vmm.h>
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#include <assert.h>
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#include <pthread.h>
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#include <stdbool.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <vmmapi.h>
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#include "acpi.h"
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#include "inout.h"
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#include "pci_emul.h"
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#include "pci_irq.h"
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#include "pci_lpc.h"
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/*
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* Implement an 8 pin PCI interrupt router compatible with the router
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* present on Intel's ICH10 chip.
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*/
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/* Fields in each PIRQ register. */
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#define PIRQ_DIS 0x80
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#define PIRQ_IRQ 0x0f
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/* Only IRQs 3-7, 9-12, and 14-15 are permitted. */
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#define PERMITTED_IRQS 0xdef8
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#define IRQ_PERMITTED(irq) (((1U << (irq)) & PERMITTED_IRQS) != 0)
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/* IRQ count to disable an IRQ. */
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#define IRQ_DISABLED 0xff
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static struct pirq {
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uint8_t reg;
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int use_count;
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int active_count;
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pthread_mutex_t lock;
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} pirqs[8];
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static u_char irq_counts[16];
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static int pirq_cold = 1;
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/*
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* Returns true if this pin is enabled with a valid IRQ. Setting the
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* register to a reserved IRQ causes interrupts to not be asserted as
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* if the pin was disabled.
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*/
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static bool
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pirq_valid_irq(int reg)
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{
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if (reg & PIRQ_DIS)
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return (false);
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return (IRQ_PERMITTED(reg & PIRQ_IRQ));
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}
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uint8_t
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pirq_read(int pin)
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{
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assert(pin > 0 && pin <= nitems(pirqs));
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return (pirqs[pin - 1].reg);
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}
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void
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pirq_write(struct vmctx *ctx, int pin, uint8_t val)
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{
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struct pirq *pirq;
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assert(pin > 0 && pin <= nitems(pirqs));
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pirq = &pirqs[pin - 1];
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pthread_mutex_lock(&pirq->lock);
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if (pirq->reg != (val & (PIRQ_DIS | PIRQ_IRQ))) {
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if (pirq->active_count != 0 && pirq_valid_irq(pirq->reg))
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vm_isa_deassert_irq(ctx, pirq->reg & PIRQ_IRQ, -1);
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pirq->reg = val & (PIRQ_DIS | PIRQ_IRQ);
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if (pirq->active_count != 0 && pirq_valid_irq(pirq->reg))
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vm_isa_assert_irq(ctx, pirq->reg & PIRQ_IRQ, -1);
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}
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pthread_mutex_unlock(&pirq->lock);
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}
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void
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pci_irq_reserve(int irq)
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{
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assert(irq < nitems(irq_counts));
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assert(pirq_cold);
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assert(irq_counts[irq] == 0 || irq_counts[irq] == IRQ_DISABLED);
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irq_counts[irq] = IRQ_DISABLED;
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}
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void
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pci_irq_use(int irq)
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{
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assert(irq < nitems(irq_counts));
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assert(pirq_cold);
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if (irq_counts[irq] != IRQ_DISABLED)
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irq_counts[irq]++;
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}
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void
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pci_irq_init(struct vmctx *ctx)
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{
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int i;
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for (i = 0; i < nitems(pirqs); i++) {
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pirqs[i].reg = PIRQ_DIS;
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pirqs[i].use_count = 0;
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pirqs[i].active_count = 0;
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pthread_mutex_init(&pirqs[i].lock, NULL);
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}
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for (i = 0; i < nitems(irq_counts); i++) {
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if (IRQ_PERMITTED(i))
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irq_counts[i] = 0;
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else
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irq_counts[i] = IRQ_DISABLED;
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}
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}
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void
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pci_irq_assert(struct pci_devinst *pi)
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{
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struct pirq *pirq;
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if (pi->pi_lintr.pirq_pin > 0) {
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assert(pi->pi_lintr.pirq_pin <= nitems(pirqs));
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pirq = &pirqs[pi->pi_lintr.pirq_pin - 1];
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pthread_mutex_lock(&pirq->lock);
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pirq->active_count++;
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if (pirq->active_count == 1 && pirq_valid_irq(pirq->reg)) {
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vm_isa_assert_irq(pi->pi_vmctx, pirq->reg & PIRQ_IRQ,
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pi->pi_lintr.ioapic_irq);
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pthread_mutex_unlock(&pirq->lock);
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return;
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}
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pthread_mutex_unlock(&pirq->lock);
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}
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vm_ioapic_assert_irq(pi->pi_vmctx, pi->pi_lintr.ioapic_irq);
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}
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void
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pci_irq_deassert(struct pci_devinst *pi)
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{
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struct pirq *pirq;
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if (pi->pi_lintr.pirq_pin > 0) {
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assert(pi->pi_lintr.pirq_pin <= nitems(pirqs));
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pirq = &pirqs[pi->pi_lintr.pirq_pin - 1];
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pthread_mutex_lock(&pirq->lock);
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pirq->active_count--;
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if (pirq->active_count == 0 && pirq_valid_irq(pirq->reg)) {
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vm_isa_deassert_irq(pi->pi_vmctx, pirq->reg & PIRQ_IRQ,
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pi->pi_lintr.ioapic_irq);
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pthread_mutex_unlock(&pirq->lock);
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return;
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}
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pthread_mutex_unlock(&pirq->lock);
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}
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vm_ioapic_deassert_irq(pi->pi_vmctx, pi->pi_lintr.ioapic_irq);
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}
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int
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pirq_alloc_pin(struct vmctx *ctx)
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{
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int best_count, best_irq, best_pin, irq, pin;
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pirq_cold = 1;
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/* First, find the least-used PIRQ pin. */
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best_pin = 0;
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best_count = pirqs[0].use_count;
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for (pin = 1; pin < nitems(pirqs); pin++) {
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if (pirqs[pin].use_count < best_count) {
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best_pin = pin;
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best_count = pirqs[pin].use_count;
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}
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}
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pirqs[best_pin].use_count++;
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/* Second, route this pin to an IRQ. */
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if (pirqs[best_pin].reg == PIRQ_DIS) {
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best_irq = -1;
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best_count = 0;
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for (irq = 0; irq < nitems(irq_counts); irq++) {
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if (irq_counts[irq] == IRQ_DISABLED)
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continue;
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if (best_irq == -1 || irq_counts[irq] < best_count) {
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best_irq = irq;
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best_count = irq_counts[irq];
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}
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}
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assert(best_irq != 0);
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irq_counts[best_irq]++;
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pirqs[best_pin].reg = best_irq;
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vm_isa_set_irq_trigger(ctx, best_irq, LEVEL_TRIGGER);
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}
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return (best_pin + 1);
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}
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int
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pirq_irq(int pin)
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{
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if (pin == -1)
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return (255);
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assert(pin > 0 && pin <= nitems(pirqs));
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return (pirqs[pin - 1].reg & PIRQ_IRQ);
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}
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/* XXX: Generate $PIR table. */
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static void
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pirq_dsdt(void)
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{
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char *irq_prs, *old;
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int irq, pin;
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irq_prs = NULL;
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for (irq = 0; irq < nitems(irq_counts); irq++) {
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if (!IRQ_PERMITTED(irq))
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continue;
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if (irq_prs == NULL)
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asprintf(&irq_prs, "%d", irq);
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else {
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old = irq_prs;
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asprintf(&irq_prs, "%s,%d", old, irq);
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free(old);
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}
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}
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/*
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* A helper method to validate a link register's value. This
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* duplicates pirq_valid_irq().
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*/
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dsdt_line("");
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dsdt_line("Method (PIRV, 1, NotSerialized)");
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dsdt_line("{");
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dsdt_line(" If (And (Arg0, 0x%02X))", PIRQ_DIS);
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dsdt_line(" {");
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dsdt_line(" Return (0x00)");
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dsdt_line(" }");
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dsdt_line(" And (Arg0, 0x%02X, Local0)", PIRQ_IRQ);
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dsdt_line(" If (LLess (Local0, 0x03))");
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dsdt_line(" {");
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dsdt_line(" Return (0x00)");
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dsdt_line(" }");
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dsdt_line(" If (LEqual (Local0, 0x08))");
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dsdt_line(" {");
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dsdt_line(" Return (0x00)");
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dsdt_line(" }");
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dsdt_line(" If (LEqual (Local0, 0x0D))");
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dsdt_line(" {");
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dsdt_line(" Return (0x00)");
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dsdt_line(" }");
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dsdt_line(" Return (0x01)");
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dsdt_line("}");
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for (pin = 0; pin < nitems(pirqs); pin++) {
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dsdt_line("");
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dsdt_line("Device (LNK%c)", 'A' + pin);
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dsdt_line("{");
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dsdt_line(" Name (_HID, EisaId (\"PNP0C0F\"))");
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dsdt_line(" Name (_UID, 0x%02X)", pin + 1);
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dsdt_line(" Method (_STA, 0, NotSerialized)");
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dsdt_line(" {");
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dsdt_line(" If (PIRV (PIR%c))", 'A' + pin);
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dsdt_line(" {");
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dsdt_line(" Return (0x0B)");
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dsdt_line(" }");
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dsdt_line(" Else");
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dsdt_line(" {");
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dsdt_line(" Return (0x09)");
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dsdt_line(" }");
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dsdt_line(" }");
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dsdt_line(" Name (_PRS, ResourceTemplate ()");
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dsdt_line(" {");
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dsdt_line(" IRQ (Level, ActiveLow, Shared, )");
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dsdt_line(" {%s}", irq_prs);
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dsdt_line(" })");
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dsdt_line(" Name (CB%02X, ResourceTemplate ()", pin + 1);
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dsdt_line(" {");
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dsdt_line(" IRQ (Level, ActiveLow, Shared, )");
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dsdt_line(" {}");
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dsdt_line(" })");
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dsdt_line(" CreateWordField (CB%02X, 0x01, CIR%c)",
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pin + 1, 'A' + pin);
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dsdt_line(" Method (_CRS, 0, NotSerialized)");
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dsdt_line(" {");
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dsdt_line(" And (PIR%c, 0x%02X, Local0)", 'A' + pin,
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PIRQ_DIS | PIRQ_IRQ);
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dsdt_line(" If (PIRV (Local0))");
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dsdt_line(" {");
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dsdt_line(" ShiftLeft (0x01, Local0, CIR%c)", 'A' + pin);
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dsdt_line(" }");
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dsdt_line(" Else");
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dsdt_line(" {");
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dsdt_line(" Store (0x00, CIR%c)", 'A' + pin);
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dsdt_line(" }");
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dsdt_line(" Return (CB%02X)", pin + 1);
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dsdt_line(" }");
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dsdt_line(" Method (_DIS, 0, NotSerialized)");
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dsdt_line(" {");
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dsdt_line(" Store (0x80, PIR%c)", 'A' + pin);
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dsdt_line(" }");
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dsdt_line(" Method (_SRS, 1, NotSerialized)");
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dsdt_line(" {");
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dsdt_line(" CreateWordField (Arg0, 0x01, SIR%c)", 'A' + pin);
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dsdt_line(" FindSetRightBit (SIR%c, Local0)", 'A' + pin);
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dsdt_line(" Store (Decrement (Local0), PIR%c)", 'A' + pin);
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dsdt_line(" }");
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dsdt_line("}");
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}
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free(irq_prs);
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}
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LPC_DSDT(pirq_dsdt);
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