b40ce02a2f
new platform module. These are probed in early boot, and have the responsibility of determining the layout of physical memory, determining the CPU timebase frequency, and handling the zoo of SMP mechanisms found on PowerPC. Reviewed by: marcel, raj Book-E parts by: raj
187 lines
4.1 KiB
C
187 lines
4.1 KiB
C
/*-
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* Copyright (c) 2008 Marcel Moolenaar
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <sys/pcpu.h>
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#include <sys/proc.h>
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#include <sys/smp.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/hid.h>
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#include <machine/intr_machdep.h>
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#include <machine/pcb.h>
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#include <machine/psl.h>
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#include <machine/smp.h>
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#include <machine/spr.h>
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#include <machine/trap_aim.h>
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#include <dev/ofw/openfirm.h>
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#include <machine/ofw_machdep.h>
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extern void *rstcode;
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extern register_t l2cr_config;
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extern register_t l3cr_config;
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void *ap_pcpu;
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static register_t
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l2_enable(void)
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{
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register_t ccr;
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ccr = mfspr(SPR_L2CR);
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if (ccr & L2CR_L2E)
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return (ccr);
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/* Configure L2 cache. */
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ccr = l2cr_config & ~L2CR_L2E;
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mtspr(SPR_L2CR, ccr | L2CR_L2I);
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do {
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ccr = mfspr(SPR_L2CR);
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} while (ccr & L2CR_L2I);
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powerpc_sync();
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mtspr(SPR_L2CR, l2cr_config);
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powerpc_sync();
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return (l2cr_config);
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}
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static register_t
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l3_enable(void)
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{
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register_t ccr;
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ccr = mfspr(SPR_L3CR);
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if (ccr & L3CR_L3E)
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return (ccr);
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/* Configure L3 cache. */
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ccr = l3cr_config & ~(L3CR_L3E | L3CR_L3I | L3CR_L3PE | L3CR_L3CLKEN);
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mtspr(SPR_L3CR, ccr);
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ccr |= 0x4000000; /* Magic, but documented. */
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mtspr(SPR_L3CR, ccr);
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ccr |= L3CR_L3CLKEN;
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mtspr(SPR_L3CR, ccr);
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mtspr(SPR_L3CR, ccr | L3CR_L3I);
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while (mfspr(SPR_L3CR) & L3CR_L3I)
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;
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mtspr(SPR_L3CR, ccr & ~L3CR_L3CLKEN);
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powerpc_sync();
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DELAY(100);
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mtspr(SPR_L3CR, ccr);
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powerpc_sync();
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DELAY(100);
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ccr |= L3CR_L3E;
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mtspr(SPR_L3CR, ccr);
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powerpc_sync();
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return(ccr);
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}
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static register_t
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l1d_enable(void)
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{
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register_t hid;
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hid = mfspr(SPR_HID0);
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if (hid & HID0_DCE)
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return (hid);
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/* Enable L1 D-cache */
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hid |= HID0_DCE;
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powerpc_sync();
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mtspr(SPR_HID0, hid | HID0_DCFI);
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powerpc_sync();
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return (hid);
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}
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static register_t
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l1i_enable(void)
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{
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register_t hid;
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hid = mfspr(SPR_HID0);
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if (hid & HID0_ICE)
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return (hid);
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/* Enable L1 I-cache */
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hid |= HID0_ICE;
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isync();
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mtspr(SPR_HID0, hid | HID0_ICFI);
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isync();
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return (hid);
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}
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uint32_t
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cpudep_ap_bootstrap(void)
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{
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uint32_t hid, msr, reg, sp;
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// reg = mfspr(SPR_MSSCR0);
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// mtspr(SPR_MSSCR0, reg | 0x3);
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__asm __volatile("mtsprg 0, %0" :: "r"(ap_pcpu));
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powerpc_sync();
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__asm __volatile("mtspr 1023,%0" :: "r"(PCPU_GET(cpuid)));
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__asm __volatile("mfspr %0,1023" : "=r"(pcpup->pc_pir));
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msr = PSL_FP | PSL_IR | PSL_DR | PSL_ME | PSL_RI;
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powerpc_sync();
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isync();
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mtmsr(msr);
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isync();
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if (l3cr_config != 0)
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reg = l3_enable();
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if (l2cr_config != 0)
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reg = l2_enable();
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reg = l1d_enable();
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reg = l1i_enable();
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hid = mfspr(SPR_HID0);
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hid &= ~(HID0_DOZE | HID0_SLEEP);
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hid |= HID0_NAP | HID0_DPM;
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mtspr(SPR_HID0, hid);
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isync();
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pcpup->pc_curthread = pcpup->pc_idlethread;
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pcpup->pc_curpcb = pcpup->pc_curthread->td_pcb;
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sp = pcpup->pc_curpcb->pcb_sp;
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return (sp);
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}
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