b4b7c60d70
The hardware always gives read access for privilege level 0, which means that we cannot use the hardware access rights and privilege level in the PTE to test whether there's a change in protection. So, we save the original vm_prot_t in the PTE as well. Add pmap_pte_prot() to set the proper access rights and privilege level on the PTE given a pmap and the requested protection. The above allows us to compare the protection in pmap_extract_and_hold() which was missing. While in pmap_extract_and_hold(), add pmap locking. While here, clean up most (i.e. all but one) PTE macros we inherited from alpha. They were either unused, used inconsistently, badly named or simply weren't beneficial. We save the wired and managed state of the PTE in distinct (bit) fields. While in pte.h, s/u_int64_t/uint64_t/g pmap locking obtained from: alc@ feedback & review by: alc@
148 lines
4.1 KiB
C
148 lines
4.1 KiB
C
/*-
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* Copyright (c) 2001 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PTE_H_
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#define _MACHINE_PTE_H_
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#ifdef LOCORE
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#define PTE_P (1<<0)
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#define PTE_MA_WB (0<<2)
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#define PTE_MA_UC (4<<2)
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#define PTE_MA_UCE (5<<2)
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#define PTE_MA_WC (6<<2)
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#define PTE_MA_NATPAGE (7<<2)
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#define PTE_A (1<<5)
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#define PTE_D (1<<6)
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#define PTE_PL_KERN (0<<7)
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#define PTE_PL_USER (3<<7)
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#define PTE_AR_R (0<<9)
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#define PTE_AR_RX (1<<9)
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#define PTE_AR_RW (2<<9)
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#define PTE_AR_RWX (3<<9)
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#define PTE_AR_R_RW (4<<9)
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#define PTE_AR_RX_RWX (5<<9)
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#define PTE_AR_RWX_RW (6<<9)
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#define PTE_AR_X_RX (7<<9)
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#else
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#define PTE_MA_WB 0
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#define PTE_MA_UC 4
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#define PTE_MA_UCE 5
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#define PTE_MA_WC 6
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#define PTE_MA_NATPAGE 7
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#define PTE_PL_KERN 0
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#define PTE_PL_USER 3
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#define PTE_AR_R 0
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#define PTE_AR_RX 1
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#define PTE_AR_RW 2
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#define PTE_AR_RWX 3
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#define PTE_AR_R_RW 4
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#define PTE_AR_RX_RWX 5
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#define PTE_AR_RWX_RW 6
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#define PTE_AR_X_RX 7
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/*
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* A short-format VHPT entry. Also matches the TLB insertion format.
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*/
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struct ia64_pte {
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uint64_t pte_p :1; /* bit 0 */
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uint64_t __rv1__ :1; /* bit 1 */
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uint64_t pte_ma :3; /* bits 2..4 */
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uint64_t pte_a :1; /* bit 5 */
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uint64_t pte_d :1; /* bit 6 */
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uint64_t pte_pl :2; /* bits 7..8 */
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uint64_t pte_ar :3; /* bits 9..11 */
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uint64_t pte_ppn :38; /* bits 12..49 */
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uint64_t __rv2__ :2; /* bits 50..51 */
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uint64_t pte_ed :1; /* bit 52 */
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/* The following bits are ignored by the hardware. */
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uint64_t pte_w :1; /* bit 53 */
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uint64_t pte_m :1; /* bit 54 */
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uint64_t pte_prot:3; /* bits 55..57 */
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uint64_t __ig__ :6; /* bits 58..63 */
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};
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/*
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* A long-format VHPT entry.
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*/
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struct ia64_lpte {
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uint64_t pte_p :1; /* bit 0 */
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uint64_t __rv1__ :1; /* bit 1 */
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uint64_t pte_ma :3; /* bits 2..4 */
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uint64_t pte_a :1; /* bit 5 */
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uint64_t pte_d :1; /* bit 6 */
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uint64_t pte_pl :2; /* bits 7..8 */
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uint64_t pte_ar :3; /* bits 9..11 */
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uint64_t pte_ppn :38; /* bits 12..49 */
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uint64_t __rv2__ :2; /* bits 50..51 */
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uint64_t pte_ed :1; /* bit 52 */
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/* The following 11 bits are ignored by the hardware. */
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uint64_t pte_w :1; /* bit 53 */
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uint64_t pte_m :1; /* bit 54 */
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uint64_t pte_prot:3; /* bits 55..57 */
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uint64_t __ig__ :6; /* bits 58..63 */
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uint64_t __rv3__ :2; /* bits 0..1 */
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uint64_t pte_ps :6; /* bits 2..7 */
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uint64_t pte_key :24; /* bits 8..31 */
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uint64_t __rv4__ :32; /* bits 32..63 */
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uint64_t pte_tag; /* includes ti */
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uint64_t pte_chain; /* pa of collision chain */
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};
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/*
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* Layout of cr.itir.
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*/
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struct ia64_itir {
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uint64_t __rv1__ :2; /* bits 0..1 */
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uint64_t itir_ps :6; /* bits 2..7 */
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uint64_t itir_key:24; /* bits 8..31 */
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uint64_t __rv2__ :32; /* bits 32..63 */
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};
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/*
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* Layout of rr[x].
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*/
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struct ia64_rr {
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uint64_t rr_ve :1; /* bit 0 */
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uint64_t __rv1__ :1; /* bit 1 */
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uint64_t rr_ps :6; /* bits 2..7 */
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uint64_t rr_rid :24; /* bits 8..31 */
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uint64_t __rv2__ :32; /* bits 32..63 */
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};
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#endif /* !LOCORE */
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#endif /* !_MACHINE_PTE_H_ */
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