500 lines
16 KiB
C
500 lines
16 KiB
C
/* $NetBSD: ncr53c9xvar.h,v 1.55 2011/07/31 18:39:00 jakllsch Exp $ */
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/*-
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* Copyright (c) 1997 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 1994 Peter Galbavy. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Peter Galbavy.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef _NCR53C9XVAR_H_
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#define _NCR53C9XVAR_H_
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#include <sys/lock.h>
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/* Set this to 1 for normal debug, or 2 for per-target tracing. */
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/* #define NCR53C9X_DEBUG 2 */
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/* Wide or differential can have 16 targets */
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#define NCR_NLUN 8
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#define NCR_ABORT_TIMEOUT 2000 /* time to wait for abort */
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#define NCR_SENSE_TIMEOUT 1000 /* time to wait for sense */
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#define FREQTOCCF(freq) (((freq + 4) / 5))
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/*
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* NCR 53c9x variants. Note these values are used as indexes into
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* a table; do not modify them unless you know what you are doing.
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*/
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#define NCR_VARIANT_ESP100 0
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#define NCR_VARIANT_ESP100A 1
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#define NCR_VARIANT_ESP200 2
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#define NCR_VARIANT_NCR53C94 3
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#define NCR_VARIANT_NCR53C96 4
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#define NCR_VARIANT_ESP406 5
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#define NCR_VARIANT_FAS408 6
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#define NCR_VARIANT_FAS216 7
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#define NCR_VARIANT_AM53C974 8
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#define NCR_VARIANT_FAS366 9
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#define NCR_VARIANT_NCR53C90_86C01 10
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#define NCR_VARIANT_FAS100A 11
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#define NCR_VARIANT_FAS236 12
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#define NCR_VARIANT_MAX 13
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/* XXX Max tag depth. Should this be defined in the register header? */
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#define NCR_TAG_DEPTH 256
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/*
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* ECB. Holds additional information for each SCSI command Comments: We
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* need a separate scsi command block because we may need to overwrite it
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* with a request sense command. Basically, we refrain from fiddling with
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* the ccb union (except do the expected updating of return values).
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* We'll generally update: ccb->ccb_h.status and ccb->csio.{resid,
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* scsi_status,sense_data}.
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*/
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struct ncr53c9x_ecb {
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/* These fields are preserved between alloc and free. */
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struct callout ch;
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struct ncr53c9x_softc *sc;
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int tag_id;
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int flags;
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union ccb *ccb; /* SCSI xfer ctrl block from above */
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TAILQ_ENTRY(ncr53c9x_ecb) free_links;
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TAILQ_ENTRY(ncr53c9x_ecb) chain;
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#define ECB_ALLOC 0x01
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#define ECB_READY 0x02
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#define ECB_SENSE 0x04
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#define ECB_ABORT 0x40
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#define ECB_RESET 0x80
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#define ECB_TENTATIVE_DONE 0x100
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int timeout;
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struct {
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uint8_t msg[3]; /* Selection Id msg and tags */
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struct scsi_generic cmd; /* SCSI command block */
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} cmd;
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uint8_t *daddr; /* Saved data pointer */
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int clen; /* Size of command in cmd.cmd */
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int dleft; /* Residue */
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uint8_t stat; /* SCSI status byte */
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uint8_t tag[2]; /* TAG bytes */
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uint8_t pad[1];
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#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1
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char trace[1000];
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#endif
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};
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#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1
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#define ECB_TRACE(ecb, msg, a, b) do { \
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const char *f = "[" msg "]"; \
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int n = strlen((ecb)->trace); \
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if (n < (sizeof((ecb)->trace)-100)) \
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sprintf((ecb)->trace + n, f, a, b); \
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} while (/* CONSTCOND */0)
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#else
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#define ECB_TRACE(ecb, msg, a, b)
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#endif
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/*
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* Some info about each (possible) target and LUN on the SCSI bus.
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*
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* SCSI I and II devices can have up to 8 LUNs, each with up to 256
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* outstanding tags. SCSI III devices have 64-bit LUN identifiers
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* that can be sparsely allocated.
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*
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* Since SCSI II devices can have up to 8 LUNs, we use an array
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* of 8 pointers to ncr53c9x_linfo structures for fast lookup.
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* Longer LUNs need to traverse the linked list.
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*/
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struct ncr53c9x_linfo {
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int64_t lun;
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LIST_ENTRY(ncr53c9x_linfo) link;
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time_t last_used;
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uint8_t used; /* # slots in use */
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uint8_t avail; /* where to start scanning */
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uint8_t busy;
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struct ncr53c9x_ecb *untagged;
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struct ncr53c9x_ecb *queued[NCR_TAG_DEPTH];
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};
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struct ncr53c9x_xinfo {
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uint8_t period;
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uint8_t offset;
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uint8_t width;
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};
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struct ncr53c9x_tinfo {
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int cmds; /* # of commands processed */
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int dconns; /* # of disconnects */
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int touts; /* # of timeouts */
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int perrs; /* # of parity errors */
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int senses; /* # of request sense commands sent */
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uint8_t flags;
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#define T_SYNCHOFF 0x01 /* SYNC mode is permanently off */
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#define T_RSELECTOFF 0x02 /* RE-SELECT mode is off */
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#define T_TAG 0x04 /* Turn on TAG QUEUEs */
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#define T_SDTRSENT 0x08 /* SDTR message has been sent to */
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#define T_WDTRSENT 0x10 /* WDTR message has been sent to */
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struct ncr53c9x_xinfo curr;
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struct ncr53c9x_xinfo goal;
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LIST_HEAD(lun_list, ncr53c9x_linfo) luns;
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struct ncr53c9x_linfo *lun[NCR_NLUN]; /* For speedy lookups */
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};
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/* Look up a lun in a tinfo */
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#define TINFO_LUN(t, l) ( \
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(((l) < NCR_NLUN) && (((t)->lun[(l)]) != NULL)) \
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? ((t)->lun[(l)]) \
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: ncr53c9x_lunsearch((t), (int64_t)(l)) \
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)
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/* Register a linenumber (for debugging). */
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#define LOGLINE(p)
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#define NCR_SHOWECBS 0x01
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#define NCR_SHOWINTS 0x02
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#define NCR_SHOWCMDS 0x04
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#define NCR_SHOWMISC 0x08
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#define NCR_SHOWTRAC 0x10
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#define NCR_SHOWSTART 0x20
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#define NCR_SHOWPHASE 0x40
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#define NCR_SHOWDMA 0x80
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#define NCR_SHOWCCMDS 0x100
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#define NCR_SHOWMSGS 0x200
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#ifdef NCR53C9X_DEBUG
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extern int ncr53c9x_debug;
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#define NCR_ECBS(str) \
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do { \
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if ((ncr53c9x_debug & NCR_SHOWECBS) != 0) \
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printf str; \
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} while (/* CONSTCOND */0)
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#define NCR_MISC(str) \
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do { \
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if ((ncr53c9x_debug & NCR_SHOWMISC) != 0) \
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printf str; \
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} while (/* CONSTCOND */0)
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#define NCR_INTS(str) \
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do { \
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if ((ncr53c9x_debug & NCR_SHOWINTS) != 0) \
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printf str; \
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} while (/* CONSTCOND */0)
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#define NCR_TRACE(str) \
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do { \
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if ((ncr53c9x_debug & NCR_SHOWTRAC) != 0) \
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printf str; \
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} while (/* CONSTCOND */0)
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#define NCR_CMDS(str) \
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do { \
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if ((ncr53c9x_debug & NCR_SHOWCMDS) != 0) \
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printf str; \
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} while (/* CONSTCOND */0)
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#define NCR_START(str) \
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do { \
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if ((ncr53c9x_debug & NCR_SHOWSTART) != 0) \
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printf str; \
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} while (/* CONSTCOND */0)
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#define NCR_PHASE(str) \
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do { \
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if ((ncr53c9x_debug & NCR_SHOWPHASE) != 0) \
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printf str; \
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} while (/* CONSTCOND */0)
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#define NCR_DMA(str) \
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do { \
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if ((ncr53c9x_debug & NCR_SHOWDMA) != 0) \
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printf str; \
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} while (/* CONSTCOND */0)
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#define NCR_MSGS(str) \
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do { \
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if ((ncr53c9x_debug & NCR_SHOWMSGS) != 0) \
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printf str; \
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} while (/* CONSTCOND */0)
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#else
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#define NCR_ECBS(str)
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#define NCR_MISC(str)
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#define NCR_INTS(str)
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#define NCR_TRACE(str)
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#define NCR_CMDS(str)
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#define NCR_START(str)
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#define NCR_PHASE(str)
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#define NCR_DMA(str)
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#define NCR_MSGS(str)
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#endif
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#define NCR_MAX_MSG_LEN 8
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struct ncr53c9x_softc;
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/*
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* Function switch used as glue to MD code
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*/
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struct ncr53c9x_glue {
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/* Mandatory entry points. */
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uint8_t (*gl_read_reg)(struct ncr53c9x_softc *, int);
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void (*gl_write_reg)(struct ncr53c9x_softc *, int, uint8_t);
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int (*gl_dma_isintr)(struct ncr53c9x_softc *);
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void (*gl_dma_reset)(struct ncr53c9x_softc *);
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int (*gl_dma_intr)(struct ncr53c9x_softc *);
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int (*gl_dma_setup)(struct ncr53c9x_softc *, void **, size_t *,
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int, size_t *);
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void (*gl_dma_go)(struct ncr53c9x_softc *);
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void (*gl_dma_stop)(struct ncr53c9x_softc *);
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int (*gl_dma_isactive)(struct ncr53c9x_softc *);
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};
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struct ncr53c9x_softc {
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device_t sc_dev; /* us as a device */
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struct cam_sim *sc_sim; /* our scsi adapter */
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struct cam_path *sc_path; /* our scsi channel */
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struct callout sc_watchdog; /* periodic timer */
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const struct ncr53c9x_glue *sc_glue; /* glue to MD code */
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int sc_cfflags; /* Copy of config flags */
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/* register defaults */
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uint8_t sc_cfg1; /* Config 1 */
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uint8_t sc_cfg2; /* Config 2, not ESP100 */
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uint8_t sc_cfg3; /* Config 3, ESP200,FAS */
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uint8_t sc_cfg3_fscsi; /* Chip-specific FSCSI bit */
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uint8_t sc_cfg4; /* Config 4, only ESP200 */
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uint8_t sc_cfg5; /* Config 5, only ESP200 */
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uint8_t sc_ccf; /* Clock Conversion */
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uint8_t sc_timeout;
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/* register copies, see ncr53c9x_readregs() */
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uint8_t sc_espintr;
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uint8_t sc_espstat;
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uint8_t sc_espstep;
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uint8_t sc_espstat2;
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uint8_t sc_espfflags;
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/* Lists of command blocks */
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TAILQ_HEAD(ecb_list, ncr53c9x_ecb) ready_list;
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struct ncr53c9x_ecb *sc_nexus; /* Current command */
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int sc_ntarg;
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struct ncr53c9x_tinfo *sc_tinfo;
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/* Data about the current nexus (updated for every cmd switch) */
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void *sc_dp; /* Current data pointer */
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ssize_t sc_dleft; /* Data left to transfer */
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/* Adapter state */
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int sc_phase; /* Copy of what bus phase we are in */
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int sc_prevphase; /* Copy of what bus phase we were in */
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uint8_t sc_state; /* State applicable to the adapter */
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uint8_t sc_flags; /* See below */
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uint8_t sc_selid;
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uint8_t sc_lastcmd;
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/* Message stuff */
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uint16_t sc_msgify; /* IDENTIFY message associated with nexus */
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uint16_t sc_msgout; /* What message is on its way out? */
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uint16_t sc_msgpriq; /* One or more messages to send (encoded) */
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uint16_t sc_msgoutq; /* What messages have been sent so far? */
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uint8_t *sc_omess; /* MSGOUT buffer */
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int sc_omess_self; /* MSGOUT buffer is self-allocated */
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void *sc_omp; /* Message pointer (for multibyte messages) */
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size_t sc_omlen;
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uint8_t *sc_imess; /* MSGIN buffer */
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int sc_imess_self; /* MSGIN buffer is self-allocated */
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void *sc_imp; /* Message pointer (for multibyte messages) */
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size_t sc_imlen;
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void *sc_cmdp; /* Command pointer (for DMAed commands) */
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size_t sc_cmdlen; /* Size of command in transit */
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/* Hardware attributes */
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int sc_freq; /* SCSI bus frequency in MHz */
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int sc_id; /* Our SCSI id */
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int sc_rev; /* Chip revision */
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int sc_features; /* Chip features */
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int sc_minsync; /* Minimum sync period / 4 */
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int sc_maxxfer; /* Maximum transfer size */
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int sc_maxoffset; /* Maximum offset */
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int sc_maxwidth; /* Maximum width */
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int sc_extended_geom; /* Should we return extended geometry */
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struct mtx sc_lock; /* driver mutex */
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struct ncr53c9x_ecb *ecb_array;
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TAILQ_HEAD(,ncr53c9x_ecb) free_list;
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};
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/* values for sc_state */
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#define NCR_IDLE 1 /* Waiting for something to do */
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#define NCR_SELECTING 2 /* SCSI command is arbiting */
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#define NCR_RESELECTED 3 /* Has been reselected */
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#define NCR_IDENTIFIED 4 /* Has gotten IFY but not TAG */
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#define NCR_CONNECTED 5 /* Actively using the SCSI bus */
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#define NCR_DISCONNECT 6 /* MSG_DISCONNECT received */
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#define NCR_CMDCOMPLETE 7 /* MSG_CMDCOMPLETE received */
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#define NCR_CLEANING 8
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#define NCR_SBR 9 /* Expect a SCSI RST because we commanded it */
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/* values for sc_flags */
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#define NCR_DROP_MSGI 0x01 /* Discard all msgs (parity err detected) */
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#define NCR_ABORTING 0x02 /* Bailing out */
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#define NCR_ICCS 0x04 /* Expect status phase results */
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#define NCR_WAITI 0x08 /* Waiting for non-DMA data to arrive */
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#define NCR_ATN 0x10 /* ATN asserted */
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#define NCR_EXPECT_ILLCMD 0x20 /* Expect Illegal Command Interrupt */
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/* values for sc_features */
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#define NCR_F_HASCFG3 0x01 /* chip has CFG3 register */
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#define NCR_F_FASTSCSI 0x02 /* chip supports Fast mode */
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#define NCR_F_DMASELECT 0x04 /* can do dmaselect */
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#define NCR_F_SELATN3 0x08 /* chip supports SELATN3 command */
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#define NCR_F_LARGEXFER 0x10 /* chip supports transfers > 64k */
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/* values for sc_msgout */
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#define SEND_DEV_RESET 0x0001
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#define SEND_PARITY_ERROR 0x0002
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#define SEND_INIT_DET_ERR 0x0004
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#define SEND_REJECT 0x0008
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#define SEND_IDENTIFY 0x0010
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#define SEND_ABORT 0x0020
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#define SEND_TAG 0x0040
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#define SEND_WDTR 0x0080
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#define SEND_SDTR 0x0100
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/* SCSI Status codes */
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#define ST_MASK 0x3e /* bit 0,6,7 is reserved */
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/* phase bits */
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#define IOI 0x01
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#define CDI 0x02
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#define MSGI 0x04
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/* Information transfer phases */
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#define DATA_OUT_PHASE (0)
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#define DATA_IN_PHASE (IOI)
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#define COMMAND_PHASE (CDI)
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#define STATUS_PHASE (CDI | IOI)
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#define MESSAGE_OUT_PHASE (MSGI | CDI)
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#define MESSAGE_IN_PHASE (MSGI | CDI | IOI)
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#define PHASE_MASK (MSGI | CDI | IOI)
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/* Some pseudo phases for getphase()*/
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#define BUSFREE_PHASE 0x100 /* Re/Selection no longer valid */
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#define INVALID_PHASE 0x101 /* Re/Selection valid, but no REQ yet */
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#define PSEUDO_PHASE 0x100 /* "pseudo" bit */
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/*
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* Macros to read and write the chip's registers.
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*/
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#define NCR_READ_REG(sc, reg) \
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(*(sc)->sc_glue->gl_read_reg)((sc), (reg))
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#define NCR_WRITE_REG(sc, reg, val) \
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(*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val))
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#ifdef NCR53C9X_DEBUG
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#define NCRCMD(sc, cmd) do { \
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if ((ncr53c9x_debug & NCR_SHOWCCMDS) != 0) \
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printf("<CMD:0x%x %d>", (unsigned int)cmd, __LINE__); \
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sc->sc_lastcmd = cmd; \
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NCR_WRITE_REG(sc, NCR_CMD, cmd); \
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} while (/* CONSTCOND */ 0)
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#else
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#define NCRCMD(sc, cmd) NCR_WRITE_REG(sc, NCR_CMD, cmd)
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#endif
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/*
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* Macros for locking
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*/
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#define NCR_LOCK_INIT(_sc) \
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mtx_init(&(_sc)->sc_lock, "ncr", "ncr53c9x lock", MTX_DEF);
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#define NCR_LOCK_INITIALIZED(_sc) mtx_initialized(&(_sc)->sc_lock)
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#define NCR_LOCK(_sc) mtx_lock(&(_sc)->sc_lock)
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#define NCR_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_lock)
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#define NCR_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_lock, (_what))
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#define NCR_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_lock)
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/*
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* DMA macros for NCR53c9x
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*/
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#define NCRDMA_ISINTR(sc) (*(sc)->sc_glue->gl_dma_isintr)((sc))
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#define NCRDMA_RESET(sc) (*(sc)->sc_glue->gl_dma_reset)((sc))
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#define NCRDMA_INTR(sc) (*(sc)->sc_glue->gl_dma_intr)((sc))
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#define NCRDMA_SETUP(sc, addr, len, datain, dmasize) \
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(*(sc)->sc_glue->gl_dma_setup)((sc), (addr), (len), (datain), (dmasize))
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#define NCRDMA_GO(sc) (*(sc)->sc_glue->gl_dma_go)((sc))
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#define NCRDMA_STOP(sc) (*(sc)->sc_glue->gl_dma_stop)((sc))
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#define NCRDMA_ISACTIVE(sc) (*(sc)->sc_glue->gl_dma_isactive)((sc))
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/*
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* Macro to convert the chip register Clock Per Byte value to
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* Synchronous Transfer Period.
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*/
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#define ncr53c9x_cpb2stp(sc, cpb) \
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((250 * (cpb)) / (sc)->sc_freq)
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extern devclass_t esp_devclass;
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int ncr53c9x_attach(struct ncr53c9x_softc *sc);
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int ncr53c9x_detach(struct ncr53c9x_softc *sc);
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void ncr53c9x_intr(void *arg);
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#endif /* _NCR53C9XVAR_H_ */
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