b5b28fc9dc
commit level triggered interrupts would work as long as the pin was not shared among multiple interrupt sources. The vlapic now keeps track of level triggered interrupts in the trigger mode register and will forward the EOI for a level triggered interrupt to the vioapic. The vioapic in turn uses the EOI to sample the level on the pin and re-inject the vector if the pin is still asserted. The vhpet is the first consumer of level triggered interrupts and advertises that it can generate interrupts on pins 20 through 23 of the vioapic. Discussed with: grehan@
202 lines
4.2 KiB
C
202 lines
4.2 KiB
C
/*-
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* Copyright (c) 2011 NetApp, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/smp.h>
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#include <x86/specialreg.h>
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#include <x86/apicreg.h>
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#include <machine/vmm.h>
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#include "vmm_ipi.h"
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#include "vmm_lapic.h"
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#include "vlapic.h"
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int
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lapic_pending_intr(struct vm *vm, int cpu)
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{
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struct vlapic *vlapic;
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vlapic = vm_lapic(vm, cpu);
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return (vlapic_pending_intr(vlapic));
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}
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void
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lapic_intr_accepted(struct vm *vm, int cpu, int vector)
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{
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struct vlapic *vlapic;
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vlapic = vm_lapic(vm, cpu);
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vlapic_intr_accepted(vlapic, vector);
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}
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int
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lapic_set_intr(struct vm *vm, int cpu, int vector, bool level)
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{
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struct vlapic *vlapic;
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if (cpu < 0 || cpu >= VM_MAXCPU)
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return (EINVAL);
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if (vector < 32 || vector > 255)
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return (EINVAL);
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vlapic = vm_lapic(vm, cpu);
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vlapic_set_intr_ready(vlapic, vector, level);
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vm_interrupt_hostcpu(vm, cpu);
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return (0);
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}
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int
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lapic_timer_tick(struct vm *vm, int cpu)
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{
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struct vlapic *vlapic;
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vlapic = vm_lapic(vm, cpu);
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return (vlapic_timer_tick(vlapic));
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}
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static boolean_t
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x2apic_msr(u_int msr)
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{
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if (msr >= 0x800 && msr <= 0xBFF)
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return (TRUE);
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else
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return (FALSE);
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}
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static u_int
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x2apic_msr_to_regoff(u_int msr)
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{
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return ((msr - 0x800) << 4);
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}
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boolean_t
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lapic_msr(u_int msr)
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{
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if (x2apic_msr(msr) || (msr == MSR_APICBASE))
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return (TRUE);
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else
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return (FALSE);
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}
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int
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lapic_rdmsr(struct vm *vm, int cpu, u_int msr, uint64_t *rval)
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{
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int error;
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u_int offset;
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struct vlapic *vlapic;
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vlapic = vm_lapic(vm, cpu);
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if (msr == MSR_APICBASE) {
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*rval = vlapic_get_apicbase(vlapic);
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error = 0;
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} else {
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offset = x2apic_msr_to_regoff(msr);
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error = vlapic_read(vlapic, offset, rval);
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}
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return (error);
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}
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int
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lapic_wrmsr(struct vm *vm, int cpu, u_int msr, uint64_t val)
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{
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int error;
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u_int offset;
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struct vlapic *vlapic;
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vlapic = vm_lapic(vm, cpu);
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if (msr == MSR_APICBASE) {
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vlapic_set_apicbase(vlapic, val);
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error = 0;
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} else {
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offset = x2apic_msr_to_regoff(msr);
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error = vlapic_write(vlapic, offset, val);
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}
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return (error);
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}
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int
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lapic_mmio_write(void *vm, int cpu, uint64_t gpa, uint64_t wval, int size,
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void *arg)
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{
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int error;
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uint64_t off;
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struct vlapic *vlapic;
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off = gpa - DEFAULT_APIC_BASE;
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/*
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* Memory mapped local apic accesses must be 4 bytes wide and
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* aligned on a 16-byte boundary.
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*/
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if (size != 4 || off & 0xf)
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return (EINVAL);
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vlapic = vm_lapic(vm, cpu);
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error = vlapic_write(vlapic, off, wval);
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return (error);
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}
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int
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lapic_mmio_read(void *vm, int cpu, uint64_t gpa, uint64_t *rval, int size,
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void *arg)
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{
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int error;
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uint64_t off;
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struct vlapic *vlapic;
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off = gpa - DEFAULT_APIC_BASE;
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/*
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* Memory mapped local apic accesses must be 4 bytes wide and
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* aligned on a 16-byte boundary.
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*/
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if (size != 4 || off & 0xf)
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return (EINVAL);
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vlapic = vm_lapic(vm, cpu);
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error = vlapic_read(vlapic, off, rval);
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return (error);
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}
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