1019 lines
36 KiB
C++
1019 lines
36 KiB
C++
///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the implementation of the FastISel class.
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//
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// "Fast" instruction selection is designed to emit very poor code quickly.
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// Also, it is not designed to be able to do much lowering, so most illegal
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// types (e.g. i64 on 32-bit targets) and operations are not supported. It is
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// also not intended to be able to do much optimization, except in a few cases
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// where doing optimizations reduces overall compile time. For example, folding
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// constants into immediate fields is often done, because it's cheap and it
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// reduces the number of instructions later phases have to examine.
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//
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// "Fast" instruction selection is able to fail gracefully and transfer
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// control to the SelectionDAG selector for operations that it doesn't
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// support. In many cases, this allows us to avoid duplicating a lot of
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// the complicated lowering logic that SelectionDAG currently has.
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//
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// The intended use for "fast" instruction selection is "-O0" mode
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// compilation, where the quality of the generated code is irrelevant when
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// weighed against the speed at which the code can be generated. Also,
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// at -O0, the LLVM optimizers are not running, and this makes the
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// compile time of codegen a much higher portion of the overall compile
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// time. Despite its limitations, "fast" instruction selection is able to
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// handle enough code on its own to provide noticeable overall speedups
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// in -O0 compiles.
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//
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// Basic operations are supported in a target-independent way, by reading
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// the same instruction descriptions that the SelectionDAG selector reads,
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// and identifying simple arithmetic operations that can be directly selected
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// from simple operators. More complicated operations currently require
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// target-specific code.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Function.h"
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#include "llvm/GlobalVariable.h"
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#include "llvm/Instructions.h"
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#include "llvm/IntrinsicInst.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/DwarfWriter.h"
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#include "llvm/Analysis/DebugInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "FunctionLoweringInfo.h"
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using namespace llvm;
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unsigned FastISel::getRegForValue(Value *V) {
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EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
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// Don't handle non-simple values in FastISel.
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if (!RealVT.isSimple())
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return 0;
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// Ignore illegal types. We must do this before looking up the value
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// in ValueMap because Arguments are given virtual registers regardless
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// of whether FastISel can handle them.
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MVT VT = RealVT.getSimpleVT();
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if (!TLI.isTypeLegal(VT)) {
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// Promote MVT::i1 to a legal type though, because it's common and easy.
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if (VT == MVT::i1)
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VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
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else
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return 0;
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}
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// Look up the value to see if we already have a register for it. We
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// cache values defined by Instructions across blocks, and other values
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// only locally. This is because Instructions already have the SSA
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// def-dominates-use requirement enforced.
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if (ValueMap.count(V))
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return ValueMap[V];
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unsigned Reg = LocalValueMap[V];
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if (Reg != 0)
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return Reg;
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if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
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if (CI->getValue().getActiveBits() <= 64)
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Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
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} else if (isa<AllocaInst>(V)) {
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Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
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} else if (isa<ConstantPointerNull>(V)) {
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// Translate this as an integer zero so that it can be
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// local-CSE'd with actual integer zeros.
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Reg =
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getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext())));
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} else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
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Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
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if (!Reg) {
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const APFloat &Flt = CF->getValueAPF();
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EVT IntVT = TLI.getPointerTy();
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uint64_t x[2];
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uint32_t IntBitWidth = IntVT.getSizeInBits();
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bool isExact;
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(void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
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APFloat::rmTowardZero, &isExact);
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if (isExact) {
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APInt IntVal(IntBitWidth, 2, x);
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unsigned IntegerReg =
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getRegForValue(ConstantInt::get(V->getContext(), IntVal));
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if (IntegerReg != 0)
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Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
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}
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}
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} else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
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if (!SelectOperator(CE, CE->getOpcode())) return 0;
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Reg = LocalValueMap[CE];
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} else if (isa<UndefValue>(V)) {
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Reg = createResultReg(TLI.getRegClassFor(VT));
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BuildMI(MBB, DL, TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
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}
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// If target-independent code couldn't handle the value, give target-specific
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// code a try.
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if (!Reg && isa<Constant>(V))
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Reg = TargetMaterializeConstant(cast<Constant>(V));
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// Don't cache constant materializations in the general ValueMap.
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// To do so would require tracking what uses they dominate.
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if (Reg != 0)
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LocalValueMap[V] = Reg;
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return Reg;
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}
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unsigned FastISel::lookUpRegForValue(Value *V) {
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// Look up the value to see if we already have a register for it. We
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// cache values defined by Instructions across blocks, and other values
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// only locally. This is because Instructions already have the SSA
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// def-dominatess-use requirement enforced.
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if (ValueMap.count(V))
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return ValueMap[V];
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return LocalValueMap[V];
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}
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/// UpdateValueMap - Update the value map to include the new mapping for this
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/// instruction, or insert an extra copy to get the result in a previous
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/// determined register.
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/// NOTE: This is only necessary because we might select a block that uses
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/// a value before we select the block that defines the value. It might be
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/// possible to fix this by selecting blocks in reverse postorder.
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unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) {
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if (!isa<Instruction>(I)) {
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LocalValueMap[I] = Reg;
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return Reg;
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}
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unsigned &AssignedReg = ValueMap[I];
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if (AssignedReg == 0)
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AssignedReg = Reg;
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else if (Reg != AssignedReg) {
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const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
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TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
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Reg, RegClass, RegClass);
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}
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return AssignedReg;
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}
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unsigned FastISel::getRegForGEPIndex(Value *Idx) {
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unsigned IdxN = getRegForValue(Idx);
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if (IdxN == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return 0;
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// If the index is smaller or larger than intptr_t, truncate or extend it.
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MVT PtrVT = TLI.getPointerTy();
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EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
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if (IdxVT.bitsLT(PtrVT))
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IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN);
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else if (IdxVT.bitsGT(PtrVT))
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IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN);
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return IdxN;
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}
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/// SelectBinaryOp - Select and emit code for a binary operator instruction,
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/// which has an opcode which directly corresponds to the given ISD opcode.
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///
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bool FastISel::SelectBinaryOp(User *I, unsigned ISDOpcode) {
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EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
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if (VT == MVT::Other || !VT.isSimple())
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// Unhandled type. Halt "fast" selection and bail.
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return false;
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// We only handle legal types. For example, on x86-32 the instruction
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// selector contains all of the 64-bit instructions from x86-64,
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// under the assumption that i64 won't be used if the target doesn't
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// support it.
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if (!TLI.isTypeLegal(VT)) {
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// MVT::i1 is special. Allow AND, OR, or XOR because they
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// don't require additional zeroing, which makes them easy.
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if (VT == MVT::i1 &&
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(ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
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ISDOpcode == ISD::XOR))
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VT = TLI.getTypeToTransformTo(I->getContext(), VT);
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else
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return false;
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}
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unsigned Op0 = getRegForValue(I->getOperand(0));
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if (Op0 == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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// Check if the second operand is a constant and handle it appropriately.
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if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
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unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
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ISDOpcode, Op0, CI->getZExtValue());
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if (ResultReg != 0) {
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// We successfully emitted code for the given LLVM Instruction.
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UpdateValueMap(I, ResultReg);
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return true;
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}
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}
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// Check if the second operand is a constant float.
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if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
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unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
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ISDOpcode, Op0, CF);
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if (ResultReg != 0) {
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// We successfully emitted code for the given LLVM Instruction.
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UpdateValueMap(I, ResultReg);
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return true;
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}
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}
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unsigned Op1 = getRegForValue(I->getOperand(1));
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if (Op1 == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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// Now we have both operands in registers. Emit the instruction.
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unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
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ISDOpcode, Op0, Op1);
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if (ResultReg == 0)
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// Target-specific code wasn't able to find a machine opcode for
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// the given ISD opcode and type. Halt "fast" selection and bail.
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return false;
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// We successfully emitted code for the given LLVM Instruction.
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UpdateValueMap(I, ResultReg);
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return true;
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}
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bool FastISel::SelectGetElementPtr(User *I) {
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unsigned N = getRegForValue(I->getOperand(0));
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if (N == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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const Type *Ty = I->getOperand(0)->getType();
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MVT VT = TLI.getPointerTy();
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for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
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OI != E; ++OI) {
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Value *Idx = *OI;
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if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
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unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
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if (Field) {
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// N = N + Offset
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uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
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// FIXME: This can be optimized by combining the add with a
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// subsequent one.
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N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
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if (N == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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}
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Ty = StTy->getElementType(Field);
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} else {
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Ty = cast<SequentialType>(Ty)->getElementType();
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// If this is a constant subscript, handle it quickly.
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if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
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if (CI->getZExtValue() == 0) continue;
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uint64_t Offs =
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TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
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N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
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if (N == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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continue;
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}
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// N = N + Idx * ElementSize;
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uint64_t ElementSize = TD.getTypeAllocSize(Ty);
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unsigned IdxN = getRegForGEPIndex(Idx);
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if (IdxN == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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if (ElementSize != 1) {
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IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
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if (IdxN == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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}
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N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
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if (N == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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}
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}
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// We successfully emitted code for the given LLVM Instruction.
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UpdateValueMap(I, N);
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return true;
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}
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bool FastISel::SelectCall(User *I) {
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Function *F = cast<CallInst>(I)->getCalledFunction();
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if (!F) return false;
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unsigned IID = F->getIntrinsicID();
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switch (IID) {
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default: break;
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case Intrinsic::dbg_declare: {
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DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
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if (!DIDescriptor::ValidDebugInfo(DI->getVariable(), CodeGenOpt::None)||!DW
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|| !DW->ShouldEmitDwarfDebug())
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return true;
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Value *Address = DI->getAddress();
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if (!Address)
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return true;
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AllocaInst *AI = dyn_cast<AllocaInst>(Address);
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// Don't handle byval struct arguments or VLAs, for example.
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if (!AI) break;
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DenseMap<const AllocaInst*, int>::iterator SI =
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StaticAllocaMap.find(AI);
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if (SI == StaticAllocaMap.end()) break; // VLAs.
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int FI = SI->second;
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if (!DI->getDebugLoc().isUnknown())
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MMI->setVariableDbgInfo(DI->getVariable(), FI, DI->getDebugLoc());
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// Building the map above is target independent. Generating DBG_VALUE
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// inline is target dependent; do this now.
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(void)TargetSelectInstruction(cast<Instruction>(I));
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return true;
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}
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case Intrinsic::dbg_value: {
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// This requires target support, but right now X86 is the only Fast target.
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DbgValueInst *DI = cast<DbgValueInst>(I);
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const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
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Value *V = DI->getValue();
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if (!V) {
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// Currently the optimizer can produce this; insert an undef to
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// help debugging. Probably the optimizer should not do this.
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BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()).
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addMetadata(DI->getVariable());
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} else if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
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BuildMI(MBB, DL, II).addImm(CI->getZExtValue()).addImm(DI->getOffset()).
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addMetadata(DI->getVariable());
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} else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
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BuildMI(MBB, DL, II).addFPImm(CF).addImm(DI->getOffset()).
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addMetadata(DI->getVariable());
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} else if (unsigned Reg = lookUpRegForValue(V)) {
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BuildMI(MBB, DL, II).addReg(Reg, RegState::Debug).addImm(DI->getOffset()).
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addMetadata(DI->getVariable());
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} else {
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// We can't yet handle anything else here because it would require
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// generating code, thus altering codegen because of debug info.
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// Insert an undef so we can see what we dropped.
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BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()).
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addMetadata(DI->getVariable());
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}
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return true;
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}
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case Intrinsic::eh_exception: {
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EVT VT = TLI.getValueType(I->getType());
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switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
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default: break;
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case TargetLowering::Expand: {
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assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!");
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unsigned Reg = TLI.getExceptionAddressRegister();
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const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
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unsigned ResultReg = createResultReg(RC);
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bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
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Reg, RC, RC);
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assert(InsertedCopy && "Can't copy address registers!");
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InsertedCopy = InsertedCopy;
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UpdateValueMap(I, ResultReg);
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return true;
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}
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}
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break;
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}
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case Intrinsic::eh_selector: {
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EVT VT = TLI.getValueType(I->getType());
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switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
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default: break;
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case TargetLowering::Expand: {
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if (MMI) {
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if (MBB->isLandingPad())
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AddCatchInfo(*cast<CallInst>(I), MMI, MBB);
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else {
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#ifndef NDEBUG
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CatchInfoLost.insert(cast<CallInst>(I));
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#endif
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// FIXME: Mark exception selector register as live in. Hack for PR1508.
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unsigned Reg = TLI.getExceptionSelectorRegister();
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if (Reg) MBB->addLiveIn(Reg);
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}
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unsigned Reg = TLI.getExceptionSelectorRegister();
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EVT SrcVT = TLI.getPointerTy();
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const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT);
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unsigned ResultReg = createResultReg(RC);
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bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Reg,
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RC, RC);
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assert(InsertedCopy && "Can't copy address registers!");
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InsertedCopy = InsertedCopy;
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// Cast the register to the type of the selector.
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if (SrcVT.bitsGT(MVT::i32))
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ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE,
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ResultReg);
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else if (SrcVT.bitsLT(MVT::i32))
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ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32,
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ISD::SIGN_EXTEND, ResultReg);
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if (ResultReg == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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UpdateValueMap(I, ResultReg);
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} else {
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unsigned ResultReg =
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getRegForValue(Constant::getNullValue(I->getType()));
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UpdateValueMap(I, ResultReg);
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}
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return true;
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}
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}
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break;
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}
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}
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return false;
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}
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bool FastISel::SelectCast(User *I, unsigned Opcode) {
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EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
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EVT DstVT = TLI.getValueType(I->getType());
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if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
|
|
DstVT == MVT::Other || !DstVT.isSimple())
|
|
// Unhandled type. Halt "fast" selection and bail.
|
|
return false;
|
|
|
|
// Check if the destination type is legal. Or as a special case,
|
|
// it may be i1 if we're doing a truncate because that's
|
|
// easy and somewhat common.
|
|
if (!TLI.isTypeLegal(DstVT))
|
|
if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
|
|
// Unhandled type. Halt "fast" selection and bail.
|
|
return false;
|
|
|
|
// Check if the source operand is legal. Or as a special case,
|
|
// it may be i1 if we're doing zero-extension because that's
|
|
// easy and somewhat common.
|
|
if (!TLI.isTypeLegal(SrcVT))
|
|
if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
|
|
// Unhandled type. Halt "fast" selection and bail.
|
|
return false;
|
|
|
|
unsigned InputReg = getRegForValue(I->getOperand(0));
|
|
if (!InputReg)
|
|
// Unhandled operand. Halt "fast" selection and bail.
|
|
return false;
|
|
|
|
// If the operand is i1, arrange for the high bits in the register to be zero.
|
|
if (SrcVT == MVT::i1) {
|
|
SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT);
|
|
InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
|
|
if (!InputReg)
|
|
return false;
|
|
}
|
|
// If the result is i1, truncate to the target's type for i1 first.
|
|
if (DstVT == MVT::i1)
|
|
DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT);
|
|
|
|
unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
|
|
DstVT.getSimpleVT(),
|
|
Opcode,
|
|
InputReg);
|
|
if (!ResultReg)
|
|
return false;
|
|
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool FastISel::SelectBitCast(User *I) {
|
|
// If the bitcast doesn't change the type, just use the operand value.
|
|
if (I->getType() == I->getOperand(0)->getType()) {
|
|
unsigned Reg = getRegForValue(I->getOperand(0));
|
|
if (Reg == 0)
|
|
return false;
|
|
UpdateValueMap(I, Reg);
|
|
return true;
|
|
}
|
|
|
|
// Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
|
|
EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
|
|
EVT DstVT = TLI.getValueType(I->getType());
|
|
|
|
if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
|
|
DstVT == MVT::Other || !DstVT.isSimple() ||
|
|
!TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
|
|
// Unhandled type. Halt "fast" selection and bail.
|
|
return false;
|
|
|
|
unsigned Op0 = getRegForValue(I->getOperand(0));
|
|
if (Op0 == 0)
|
|
// Unhandled operand. Halt "fast" selection and bail.
|
|
return false;
|
|
|
|
// First, try to perform the bitcast by inserting a reg-reg copy.
|
|
unsigned ResultReg = 0;
|
|
if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
|
|
TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
|
|
TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
|
|
ResultReg = createResultReg(DstClass);
|
|
|
|
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
|
|
Op0, DstClass, SrcClass);
|
|
if (!InsertedCopy)
|
|
ResultReg = 0;
|
|
}
|
|
|
|
// If the reg-reg copy failed, select a BIT_CONVERT opcode.
|
|
if (!ResultReg)
|
|
ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
|
|
ISD::BIT_CONVERT, Op0);
|
|
|
|
if (!ResultReg)
|
|
return false;
|
|
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool
|
|
FastISel::SelectInstruction(Instruction *I) {
|
|
// First, try doing target-independent selection.
|
|
if (SelectOperator(I, I->getOpcode()))
|
|
return true;
|
|
|
|
// Next, try calling the target to attempt to handle the instruction.
|
|
if (TargetSelectInstruction(I))
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
/// FastEmitBranch - Emit an unconditional branch to the given block,
|
|
/// unless it is the immediate (fall-through) successor, and update
|
|
/// the CFG.
|
|
void
|
|
FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
|
|
if (MBB->isLayoutSuccessor(MSucc)) {
|
|
// The unconditional fall-through case, which needs no instructions.
|
|
} else {
|
|
// The unconditional branch case.
|
|
TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
|
|
}
|
|
MBB->addSuccessor(MSucc);
|
|
}
|
|
|
|
/// SelectFNeg - Emit an FNeg operation.
|
|
///
|
|
bool
|
|
FastISel::SelectFNeg(User *I) {
|
|
unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
|
|
if (OpReg == 0) return false;
|
|
|
|
// If the target has ISD::FNEG, use it.
|
|
EVT VT = TLI.getValueType(I->getType());
|
|
unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(),
|
|
ISD::FNEG, OpReg);
|
|
if (ResultReg != 0) {
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
// Bitcast the value to integer, twiddle the sign bit with xor,
|
|
// and then bitcast it back to floating-point.
|
|
if (VT.getSizeInBits() > 64) return false;
|
|
EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
|
|
if (!TLI.isTypeLegal(IntVT))
|
|
return false;
|
|
|
|
unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
|
|
ISD::BIT_CONVERT, OpReg);
|
|
if (IntReg == 0)
|
|
return false;
|
|
|
|
unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, IntReg,
|
|
UINT64_C(1) << (VT.getSizeInBits()-1),
|
|
IntVT.getSimpleVT());
|
|
if (IntResultReg == 0)
|
|
return false;
|
|
|
|
ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(),
|
|
ISD::BIT_CONVERT, IntResultReg);
|
|
if (ResultReg == 0)
|
|
return false;
|
|
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool
|
|
FastISel::SelectOperator(User *I, unsigned Opcode) {
|
|
switch (Opcode) {
|
|
case Instruction::Add:
|
|
return SelectBinaryOp(I, ISD::ADD);
|
|
case Instruction::FAdd:
|
|
return SelectBinaryOp(I, ISD::FADD);
|
|
case Instruction::Sub:
|
|
return SelectBinaryOp(I, ISD::SUB);
|
|
case Instruction::FSub:
|
|
// FNeg is currently represented in LLVM IR as a special case of FSub.
|
|
if (BinaryOperator::isFNeg(I))
|
|
return SelectFNeg(I);
|
|
return SelectBinaryOp(I, ISD::FSUB);
|
|
case Instruction::Mul:
|
|
return SelectBinaryOp(I, ISD::MUL);
|
|
case Instruction::FMul:
|
|
return SelectBinaryOp(I, ISD::FMUL);
|
|
case Instruction::SDiv:
|
|
return SelectBinaryOp(I, ISD::SDIV);
|
|
case Instruction::UDiv:
|
|
return SelectBinaryOp(I, ISD::UDIV);
|
|
case Instruction::FDiv:
|
|
return SelectBinaryOp(I, ISD::FDIV);
|
|
case Instruction::SRem:
|
|
return SelectBinaryOp(I, ISD::SREM);
|
|
case Instruction::URem:
|
|
return SelectBinaryOp(I, ISD::UREM);
|
|
case Instruction::FRem:
|
|
return SelectBinaryOp(I, ISD::FREM);
|
|
case Instruction::Shl:
|
|
return SelectBinaryOp(I, ISD::SHL);
|
|
case Instruction::LShr:
|
|
return SelectBinaryOp(I, ISD::SRL);
|
|
case Instruction::AShr:
|
|
return SelectBinaryOp(I, ISD::SRA);
|
|
case Instruction::And:
|
|
return SelectBinaryOp(I, ISD::AND);
|
|
case Instruction::Or:
|
|
return SelectBinaryOp(I, ISD::OR);
|
|
case Instruction::Xor:
|
|
return SelectBinaryOp(I, ISD::XOR);
|
|
|
|
case Instruction::GetElementPtr:
|
|
return SelectGetElementPtr(I);
|
|
|
|
case Instruction::Br: {
|
|
BranchInst *BI = cast<BranchInst>(I);
|
|
|
|
if (BI->isUnconditional()) {
|
|
BasicBlock *LLVMSucc = BI->getSuccessor(0);
|
|
MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
|
|
FastEmitBranch(MSucc);
|
|
return true;
|
|
}
|
|
|
|
// Conditional branches are not handed yet.
|
|
// Halt "fast" selection and bail.
|
|
return false;
|
|
}
|
|
|
|
case Instruction::Unreachable:
|
|
// Nothing to emit.
|
|
return true;
|
|
|
|
case Instruction::PHI:
|
|
// PHI nodes are already emitted.
|
|
return true;
|
|
|
|
case Instruction::Alloca:
|
|
// FunctionLowering has the static-sized case covered.
|
|
if (StaticAllocaMap.count(cast<AllocaInst>(I)))
|
|
return true;
|
|
|
|
// Dynamic-sized alloca is not handled yet.
|
|
return false;
|
|
|
|
case Instruction::Call:
|
|
return SelectCall(I);
|
|
|
|
case Instruction::BitCast:
|
|
return SelectBitCast(I);
|
|
|
|
case Instruction::FPToSI:
|
|
return SelectCast(I, ISD::FP_TO_SINT);
|
|
case Instruction::ZExt:
|
|
return SelectCast(I, ISD::ZERO_EXTEND);
|
|
case Instruction::SExt:
|
|
return SelectCast(I, ISD::SIGN_EXTEND);
|
|
case Instruction::Trunc:
|
|
return SelectCast(I, ISD::TRUNCATE);
|
|
case Instruction::SIToFP:
|
|
return SelectCast(I, ISD::SINT_TO_FP);
|
|
|
|
case Instruction::IntToPtr: // Deliberate fall-through.
|
|
case Instruction::PtrToInt: {
|
|
EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
|
|
EVT DstVT = TLI.getValueType(I->getType());
|
|
if (DstVT.bitsGT(SrcVT))
|
|
return SelectCast(I, ISD::ZERO_EXTEND);
|
|
if (DstVT.bitsLT(SrcVT))
|
|
return SelectCast(I, ISD::TRUNCATE);
|
|
unsigned Reg = getRegForValue(I->getOperand(0));
|
|
if (Reg == 0) return false;
|
|
UpdateValueMap(I, Reg);
|
|
return true;
|
|
}
|
|
|
|
default:
|
|
// Unhandled instruction. Halt "fast" selection and bail.
|
|
return false;
|
|
}
|
|
}
|
|
|
|
FastISel::FastISel(MachineFunction &mf,
|
|
MachineModuleInfo *mmi,
|
|
DwarfWriter *dw,
|
|
DenseMap<const Value *, unsigned> &vm,
|
|
DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
|
|
DenseMap<const AllocaInst *, int> &am
|
|
#ifndef NDEBUG
|
|
, SmallSet<Instruction*, 8> &cil
|
|
#endif
|
|
)
|
|
: MBB(0),
|
|
ValueMap(vm),
|
|
MBBMap(bm),
|
|
StaticAllocaMap(am),
|
|
#ifndef NDEBUG
|
|
CatchInfoLost(cil),
|
|
#endif
|
|
MF(mf),
|
|
MMI(mmi),
|
|
DW(dw),
|
|
MRI(MF.getRegInfo()),
|
|
MFI(*MF.getFrameInfo()),
|
|
MCP(*MF.getConstantPool()),
|
|
TM(MF.getTarget()),
|
|
TD(*TM.getTargetData()),
|
|
TII(*TM.getInstrInfo()),
|
|
TLI(*TM.getTargetLowering()) {
|
|
}
|
|
|
|
FastISel::~FastISel() {}
|
|
|
|
unsigned FastISel::FastEmit_(MVT, MVT,
|
|
unsigned) {
|
|
return 0;
|
|
}
|
|
|
|
unsigned FastISel::FastEmit_r(MVT, MVT,
|
|
unsigned, unsigned /*Op0*/) {
|
|
return 0;
|
|
}
|
|
|
|
unsigned FastISel::FastEmit_rr(MVT, MVT,
|
|
unsigned, unsigned /*Op0*/,
|
|
unsigned /*Op0*/) {
|
|
return 0;
|
|
}
|
|
|
|
unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
|
|
return 0;
|
|
}
|
|
|
|
unsigned FastISel::FastEmit_f(MVT, MVT,
|
|
unsigned, ConstantFP * /*FPImm*/) {
|
|
return 0;
|
|
}
|
|
|
|
unsigned FastISel::FastEmit_ri(MVT, MVT,
|
|
unsigned, unsigned /*Op0*/,
|
|
uint64_t /*Imm*/) {
|
|
return 0;
|
|
}
|
|
|
|
unsigned FastISel::FastEmit_rf(MVT, MVT,
|
|
unsigned, unsigned /*Op0*/,
|
|
ConstantFP * /*FPImm*/) {
|
|
return 0;
|
|
}
|
|
|
|
unsigned FastISel::FastEmit_rri(MVT, MVT,
|
|
unsigned,
|
|
unsigned /*Op0*/, unsigned /*Op1*/,
|
|
uint64_t /*Imm*/) {
|
|
return 0;
|
|
}
|
|
|
|
/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
|
|
/// to emit an instruction with an immediate operand using FastEmit_ri.
|
|
/// If that fails, it materializes the immediate into a register and try
|
|
/// FastEmit_rr instead.
|
|
unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode,
|
|
unsigned Op0, uint64_t Imm,
|
|
MVT ImmType) {
|
|
// First check if immediate type is legal. If not, we can't use the ri form.
|
|
unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
|
|
if (ResultReg != 0)
|
|
return ResultReg;
|
|
unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
|
|
if (MaterialReg == 0)
|
|
return 0;
|
|
return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
|
|
}
|
|
|
|
/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
|
|
/// to emit an instruction with a floating-point immediate operand using
|
|
/// FastEmit_rf. If that fails, it materializes the immediate into a register
|
|
/// and try FastEmit_rr instead.
|
|
unsigned FastISel::FastEmit_rf_(MVT VT, unsigned Opcode,
|
|
unsigned Op0, ConstantFP *FPImm,
|
|
MVT ImmType) {
|
|
// First check if immediate type is legal. If not, we can't use the rf form.
|
|
unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
|
|
if (ResultReg != 0)
|
|
return ResultReg;
|
|
|
|
// Materialize the constant in a register.
|
|
unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
|
|
if (MaterialReg == 0) {
|
|
// If the target doesn't have a way to directly enter a floating-point
|
|
// value into a register, use an alternate approach.
|
|
// TODO: The current approach only supports floating-point constants
|
|
// that can be constructed by conversion from integer values. This should
|
|
// be replaced by code that creates a load from a constant-pool entry,
|
|
// which will require some target-specific work.
|
|
const APFloat &Flt = FPImm->getValueAPF();
|
|
EVT IntVT = TLI.getPointerTy();
|
|
|
|
uint64_t x[2];
|
|
uint32_t IntBitWidth = IntVT.getSizeInBits();
|
|
bool isExact;
|
|
(void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
|
|
APFloat::rmTowardZero, &isExact);
|
|
if (!isExact)
|
|
return 0;
|
|
APInt IntVal(IntBitWidth, 2, x);
|
|
|
|
unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
|
|
ISD::Constant, IntVal.getZExtValue());
|
|
if (IntegerReg == 0)
|
|
return 0;
|
|
MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
|
|
ISD::SINT_TO_FP, IntegerReg);
|
|
if (MaterialReg == 0)
|
|
return 0;
|
|
}
|
|
return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
|
|
}
|
|
|
|
unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
|
|
return MRI.createVirtualRegister(RC);
|
|
}
|
|
|
|
unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
|
|
const TargetRegisterClass* RC) {
|
|
unsigned ResultReg = createResultReg(RC);
|
|
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
|
|
|
|
BuildMI(MBB, DL, II, ResultReg);
|
|
return ResultReg;
|
|
}
|
|
|
|
unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
|
|
const TargetRegisterClass *RC,
|
|
unsigned Op0) {
|
|
unsigned ResultReg = createResultReg(RC);
|
|
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
|
|
|
|
if (II.getNumDefs() >= 1)
|
|
BuildMI(MBB, DL, II, ResultReg).addReg(Op0);
|
|
else {
|
|
BuildMI(MBB, DL, II).addReg(Op0);
|
|
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
|
|
II.ImplicitDefs[0], RC, RC);
|
|
if (!InsertedCopy)
|
|
ResultReg = 0;
|
|
}
|
|
|
|
return ResultReg;
|
|
}
|
|
|
|
unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
|
|
const TargetRegisterClass *RC,
|
|
unsigned Op0, unsigned Op1) {
|
|
unsigned ResultReg = createResultReg(RC);
|
|
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
|
|
|
|
if (II.getNumDefs() >= 1)
|
|
BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1);
|
|
else {
|
|
BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1);
|
|
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
|
|
II.ImplicitDefs[0], RC, RC);
|
|
if (!InsertedCopy)
|
|
ResultReg = 0;
|
|
}
|
|
return ResultReg;
|
|
}
|
|
|
|
unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
|
|
const TargetRegisterClass *RC,
|
|
unsigned Op0, uint64_t Imm) {
|
|
unsigned ResultReg = createResultReg(RC);
|
|
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
|
|
|
|
if (II.getNumDefs() >= 1)
|
|
BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm);
|
|
else {
|
|
BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm);
|
|
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
|
|
II.ImplicitDefs[0], RC, RC);
|
|
if (!InsertedCopy)
|
|
ResultReg = 0;
|
|
}
|
|
return ResultReg;
|
|
}
|
|
|
|
unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
|
|
const TargetRegisterClass *RC,
|
|
unsigned Op0, ConstantFP *FPImm) {
|
|
unsigned ResultReg = createResultReg(RC);
|
|
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
|
|
|
|
if (II.getNumDefs() >= 1)
|
|
BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm);
|
|
else {
|
|
BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm);
|
|
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
|
|
II.ImplicitDefs[0], RC, RC);
|
|
if (!InsertedCopy)
|
|
ResultReg = 0;
|
|
}
|
|
return ResultReg;
|
|
}
|
|
|
|
unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
|
|
const TargetRegisterClass *RC,
|
|
unsigned Op0, unsigned Op1, uint64_t Imm) {
|
|
unsigned ResultReg = createResultReg(RC);
|
|
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
|
|
|
|
if (II.getNumDefs() >= 1)
|
|
BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
|
|
else {
|
|
BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm);
|
|
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
|
|
II.ImplicitDefs[0], RC, RC);
|
|
if (!InsertedCopy)
|
|
ResultReg = 0;
|
|
}
|
|
return ResultReg;
|
|
}
|
|
|
|
unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
|
|
const TargetRegisterClass *RC,
|
|
uint64_t Imm) {
|
|
unsigned ResultReg = createResultReg(RC);
|
|
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
|
|
|
|
if (II.getNumDefs() >= 1)
|
|
BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
|
|
else {
|
|
BuildMI(MBB, DL, II).addImm(Imm);
|
|
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
|
|
II.ImplicitDefs[0], RC, RC);
|
|
if (!InsertedCopy)
|
|
ResultReg = 0;
|
|
}
|
|
return ResultReg;
|
|
}
|
|
|
|
unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
|
|
unsigned Op0, uint32_t Idx) {
|
|
const TargetRegisterClass* RC = MRI.getRegClass(Op0);
|
|
|
|
unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
|
|
const TargetInstrDesc &II = TII.get(TargetOpcode::EXTRACT_SUBREG);
|
|
|
|
if (II.getNumDefs() >= 1)
|
|
BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx);
|
|
else {
|
|
BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx);
|
|
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
|
|
II.ImplicitDefs[0], RC, RC);
|
|
if (!InsertedCopy)
|
|
ResultReg = 0;
|
|
}
|
|
return ResultReg;
|
|
}
|
|
|
|
/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
|
|
/// with all but the least significant bit set to zero.
|
|
unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op) {
|
|
return FastEmit_ri(VT, VT, ISD::AND, Op, 1);
|
|
}
|