62a65a654e
This re-use the framework established for SSE2, SSSE3 and AVX2. However, GCC is using FP registers on Aarch64, so unlike SSE/AVX2 we can't rely on the registers being left alone between ASM statements. So instead, the NEON code uses C variables and GCC extended ASM syntax. Note that since the kernel explicitly disable vector registers, they have to be locally re-enabled explicitly. As we use the variable's number to define the symbolic name, and GCC won't allow duplicate symbolic names, numbers have to be unique. Even when the code is not going to be used (e.g. the case for 4 registers when using the macro with only 2). Only the actually used variables should be declared, otherwise the build will fails in debug mode. This requires the replacement of the XOR(X,X) syntax by a new ZERO(X) macro, which does the same thing but without repeating the argument. And perhaps someday there will be a machine where there is a more efficient way to zero a register than XOR with itself. This affects scalar, SSE2, SSSE3 and AVX2 as they need the new macro. It's possible to write faster implementations (different scheduling, different unrolling, interleaving NEON and scalar, ...) for various cores, but this one has the advantage of fitting in the current state of the code, and thus is likely easier to review/check/merge. The only difference between aarch64-neon and aarch64-neonx2 is that aarch64-neonx2 unroll some functions some more. Reviewed-by: Gvozden Neskovic <neskovic@gmail.com> Reviewed-by: Brian Behlendorf <behlendorf1@llnl.gov> Signed-off-by: Romain Dolbeau <romain.dolbeau@atos.net> Closes #4801
165 lines
4.1 KiB
C
165 lines
4.1 KiB
C
/*
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* CDDL HEADER START
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*
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* The contents of this file are subject to the terms of the
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* Common Development and Distribution License (the "License").
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* You may not use this file except in compliance with the License.
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*
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* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
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* or http://www.opensolaris.org/os/licensing.
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* See the License for the specific language governing permissions
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* and limitations under the License.
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*
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* When distributing Covered Code, include this CDDL HEADER in each
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* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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* If applicable, add the following below this CDDL HEADER, with the
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* fields enclosed by brackets "[]" replaced with your own identifying
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* information: Portions Copyright [yyyy] [name of copyright owner]
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*
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* CDDL HEADER END
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*/
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/*
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* Copyright (C) 2016 Romain Dolbeau. All rights reserved.
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*/
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#include <sys/isa_defs.h>
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#if defined(__aarch64__)
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#include "vdev_raidz_math_aarch64_neon_common.h"
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#define GEN_P_DEFINE() \
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GEN_X_DEFINE_0_3() \
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GEN_X_DEFINE_4_5() \
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GEN_X_DEFINE_6_7()
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#define GEN_P_STRIDE 8
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#define GEN_P_P 0, 1, 2, 3, 4, 5, 6, 7
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#define GEN_PQ_DEFINE() \
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GEN_X_DEFINE_0_3() \
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GEN_X_DEFINE_4_5() \
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GEN_X_DEFINE_6_7() \
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GEN_X_DEFINE_8_9() \
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GEN_X_DEFINE_10_11() \
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GEN_X_DEFINE_16() \
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GEN_X_DEFINE_17() \
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GEN_X_DEFINE_33_36()
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#define GEN_PQ_STRIDE 4
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#define GEN_PQ_D 0, 1, 2, 3
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#define GEN_PQ_P 4, 5, 6, 7
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#define GEN_PQ_Q 8, 9, 10, 11
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#define GEN_PQR_DEFINE() \
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GEN_X_DEFINE_0_3() \
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GEN_X_DEFINE_4_5() \
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GEN_X_DEFINE_6_7() \
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GEN_X_DEFINE_8_9() \
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GEN_X_DEFINE_22_23() \
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GEN_X_DEFINE_24_27() \
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GEN_X_DEFINE_16() \
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GEN_X_DEFINE_17() \
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GEN_X_DEFINE_33_36()
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#define GEN_PQR_STRIDE 4
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#define GEN_PQR_D 0, 1, 2, 3
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#define GEN_PQR_P 4, 5, 6, 7
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#define GEN_PQR_Q 8, 9, 22, 23
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#define GEN_PQR_R 24, 25, 26, 27
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#define REC_P_DEFINE() \
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GEN_X_DEFINE_0_3() \
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GEN_X_DEFINE_33_36()
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#define REC_P_STRIDE 4
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#define REC_P_X 0, 1, 2, 3
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#define REC_Q_DEFINE() \
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GEN_X_DEFINE_0_3() \
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GEN_X_DEFINE_16() \
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GEN_X_DEFINE_17() \
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GEN_X_DEFINE_33_36()
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#define REC_Q_STRIDE 4
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#define REC_Q_X 0, 1, 2, 3
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#define REC_R_DEFINE() \
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GEN_X_DEFINE_0_3() \
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GEN_X_DEFINE_16() \
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GEN_X_DEFINE_17() \
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GEN_X_DEFINE_33_36()
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#define REC_R_STRIDE 4
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#define REC_R_X 0, 1, 2, 3
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#define REC_PQ_DEFINE() \
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GEN_X_DEFINE_0_3() \
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GEN_X_DEFINE_4_5() \
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GEN_X_DEFINE_6_7() \
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GEN_X_DEFINE_8_9() \
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GEN_X_DEFINE_16() \
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GEN_X_DEFINE_17() \
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GEN_X_DEFINE_22_23() \
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GEN_X_DEFINE_33_36()
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#define REC_PQ_STRIDE 4
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#define REC_PQ_X 0, 1, 2, 3
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#define REC_PQ_Y 4, 5, 6, 7
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#define REC_PQ_D 8, 9, 22, 23
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#define REC_PR_DEFINE() REC_PQ_DEFINE()
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#define REC_PR_STRIDE 4
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#define REC_PR_X 0, 1, 2, 3
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#define REC_PR_Y 4, 5, 6, 7
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#define REC_PR_D 8, 9, 22, 23
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#define REC_QR_DEFINE() REC_PQ_DEFINE()
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#define REC_QR_STRIDE 4
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#define REC_QR_X 0, 1, 2, 3
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#define REC_QR_Y 4, 5, 6, 7
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#define REC_QR_D 8, 9, 22, 23
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#define REC_PQR_DEFINE() \
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GEN_X_DEFINE_0_3() \
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GEN_X_DEFINE_4_5() \
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GEN_X_DEFINE_6_7() \
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GEN_X_DEFINE_8_9() \
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GEN_X_DEFINE_16() \
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GEN_X_DEFINE_17() \
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GEN_X_DEFINE_22_23() \
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GEN_X_DEFINE_24_27() \
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GEN_X_DEFINE_28_30() \
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GEN_X_DEFINE_31() \
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GEN_X_DEFINE_33_36()
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#define REC_PQR_STRIDE 4
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#define REC_PQR_X 0, 1, 2, 3
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#define REC_PQR_Y 4, 5, 6, 7
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#define REC_PQR_Z 8, 9, 22, 23
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#define REC_PQR_D 24, 25, 26, 27
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#define REC_PQR_XS 24, 25, 26, 27
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#define REC_PQR_YS 28, 29, 30, 31
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#include <sys/vdev_raidz_impl.h>
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#include "vdev_raidz_math_impl.h"
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DEFINE_GEN_METHODS(aarch64_neonx2);
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/*
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* If compiled with -O0, gcc doesn't do any stack frame coalescing
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* and -Wframe-larger-than=1024 is triggered in debug mode.
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*/
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#pragma GCC diagnostic ignored "-Wframe-larger-than="
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DEFINE_REC_METHODS(aarch64_neonx2);
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#pragma GCC diagnostic pop
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static boolean_t
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raidz_will_aarch64_neonx2_work(void)
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{
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return (B_TRUE); // __arch64__ requires NEON
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}
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const raidz_impl_ops_t vdev_raidz_aarch64_neonx2_impl = {
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.init = NULL,
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.fini = NULL,
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.gen = RAIDZ_GEN_METHODS(aarch64_neonx2),
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.rec = RAIDZ_REC_METHODS(aarch64_neonx2),
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.is_supported = &raidz_will_aarch64_neonx2_work,
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.name = "aarch64_neonx2"
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};
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#endif /* defined(__aarch64__) */
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