c821a62f9c
be able to claim I know how the UART code works." * Just return 115200 as the current baud rate. I should cache it in the device struct and return that but I'm lazy right now. * don't error out on other ioctl settings for now, just silently ignore them. * remove some code that was copied from the 8250 driver that isn't needed any longer. Tested: * AR9331, Carambola-2 board.
738 lines
17 KiB
C
738 lines
17 KiB
C
/*-
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* Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <machine/bus.h>
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_cpu.h>
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#include <dev/uart/uart_bus.h>
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#include <mips/atheros/ar933x_uart.h>
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#include "uart_if.h"
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/*
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* Default system clock is 25MHz; see ar933x_chip.c for how
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* the startup process determines whether it's 25MHz or 40MHz.
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*/
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#define DEFAULT_RCLK (25 * 1000 * 1000)
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#define ar933x_getreg(bas, reg) \
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bus_space_read_4((bas)->bst, (bas)->bsh, reg)
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#define ar933x_setreg(bas, reg, value) \
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bus_space_write_4((bas)->bst, (bas)->bsh, reg, value)
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static int
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ar933x_drain(struct uart_bas *bas, int what)
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{
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int limit;
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if (what & UART_DRAIN_TRANSMITTER) {
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limit = 10*1024;
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/* Loop over until the TX FIFO shows entirely clear */
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while (--limit) {
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if ((ar933x_getreg(bas, AR933X_UART_CS_REG)
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& AR933X_UART_CS_TX_BUSY) == 0)
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break;
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}
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if (limit == 0) {
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return (EIO);
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}
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}
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if (what & UART_DRAIN_RECEIVER) {
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limit=10*4096;
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while (--limit) {
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/* XXX duplicated from ar933x_getc() */
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/* XXX TODO: refactor! */
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/* If there's nothing to read, stop! */
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if ((ar933x_getreg(bas, AR933X_UART_DATA_REG) &
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AR933X_UART_DATA_RX_CSR) == 0) {
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break;
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}
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/* Read the top of the RX FIFO */
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(void) ar933x_getreg(bas, AR933X_UART_DATA_REG);
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/* Remove that entry from said RX FIFO */
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ar933x_setreg(bas, AR933X_UART_DATA_REG,
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AR933X_UART_DATA_RX_CSR);
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uart_barrier(bas);
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DELAY(2);
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}
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if (limit == 0) {
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return (EIO);
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}
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}
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return (0);
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}
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/*
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* Calculate the baud from the given chip configuration parameters.
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*/
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static unsigned long
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ar933x_uart_get_baud(unsigned int clk, unsigned int scale,
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unsigned int step)
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{
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uint64_t t;
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uint32_t div;
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div = (2 << 16) * (scale + 1);
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t = clk;
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t *= step;
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t += (div / 2);
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t = t / div;
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return (t);
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}
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/*
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* Calculate the scale/step with the lowest possible deviation from
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* the target baudrate.
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*/
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static void
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ar933x_uart_get_scale_step(struct uart_bas *bas, unsigned int baud,
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unsigned int *scale, unsigned int *step)
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{
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unsigned int tscale;
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uint32_t clk;
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long min_diff;
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clk = bas->rclk;
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*scale = 0;
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*step = 0;
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min_diff = baud;
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for (tscale = 0; tscale < AR933X_UART_MAX_SCALE; tscale++) {
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uint64_t tstep;
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int diff;
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tstep = baud * (tscale + 1);
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tstep *= (2 << 16);
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tstep = tstep / clk;
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if (tstep > AR933X_UART_MAX_STEP)
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break;
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diff = abs(ar933x_uart_get_baud(clk, tscale, tstep) - baud);
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if (diff < min_diff) {
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min_diff = diff;
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*scale = tscale;
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*step = tstep;
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}
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}
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}
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static int
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ar933x_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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/* UART always 8 bits */
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/* UART always 1 stop bit */
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/* UART parity is controllable by bits 0:1, ignore for now */
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/* Set baudrate if required. */
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if (baudrate > 0) {
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uint32_t clock_scale, clock_step;
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/* Find the best fit for the given baud rate */
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ar933x_uart_get_scale_step(bas, baudrate, &clock_scale,
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&clock_step);
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/*
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* Program the clock register in its entirety - no need
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* for Read-Modify-Write.
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*/
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ar933x_setreg(bas, AR933X_UART_CLOCK_REG,
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((clock_scale & AR933X_UART_CLOCK_SCALE_M)
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<< AR933X_UART_CLOCK_SCALE_S) |
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(clock_step & AR933X_UART_CLOCK_STEP_M));
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}
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uart_barrier(bas);
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return (0);
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}
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/*
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* Low-level UART interface.
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*/
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static int ar933x_probe(struct uart_bas *bas);
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static void ar933x_init(struct uart_bas *bas, int, int, int, int);
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static void ar933x_term(struct uart_bas *bas);
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static void ar933x_putc(struct uart_bas *bas, int);
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static int ar933x_rxready(struct uart_bas *bas);
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static int ar933x_getc(struct uart_bas *bas, struct mtx *);
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static struct uart_ops uart_ar933x_ops = {
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.probe = ar933x_probe,
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.init = ar933x_init,
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.term = ar933x_term,
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.putc = ar933x_putc,
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.rxready = ar933x_rxready,
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.getc = ar933x_getc,
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};
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static int
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ar933x_probe(struct uart_bas *bas)
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{
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/* We always know this will be here */
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return (0);
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}
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static void
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ar933x_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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uint32_t reg;
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/* Setup default parameters */
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ar933x_param(bas, baudrate, databits, stopbits, parity);
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/* XXX Force enable UART in case it was disabled */
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/* Disable all interrupts */
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ar933x_setreg(bas, AR933X_UART_INT_EN_REG, 0x00000000);
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/* Disable the host interrupt */
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reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
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reg &= ~AR933X_UART_CS_HOST_INT_EN;
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ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
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uart_barrier(bas);
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/* XXX Set RTS/DTR? */
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}
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/*
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* Detach from console.
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*/
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static void
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ar933x_term(struct uart_bas *bas)
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{
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/* XXX TODO */
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}
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static void
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ar933x_putc(struct uart_bas *bas, int c)
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{
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int limit;
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limit = 250000;
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/* Wait for space in the TX FIFO */
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while ( ((ar933x_getreg(bas, AR933X_UART_DATA_REG) &
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AR933X_UART_DATA_TX_CSR) == 0) && --limit)
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DELAY(4);
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/* Write the actual byte */
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ar933x_setreg(bas, AR933X_UART_DATA_REG,
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(c & 0xff) | AR933X_UART_DATA_TX_CSR);
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}
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static int
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ar933x_rxready(struct uart_bas *bas)
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{
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/* Wait for a character to come ready */
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return (!!(ar933x_getreg(bas, AR933X_UART_DATA_REG)
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& AR933X_UART_DATA_RX_CSR));
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}
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static int
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ar933x_getc(struct uart_bas *bas, struct mtx *hwmtx)
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{
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int c;
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uart_lock(hwmtx);
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/* Wait for a character to come ready */
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while ((ar933x_getreg(bas, AR933X_UART_DATA_REG) &
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AR933X_UART_DATA_RX_CSR) == 0) {
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uart_unlock(hwmtx);
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DELAY(4);
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uart_lock(hwmtx);
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}
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/* Read the top of the RX FIFO */
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c = ar933x_getreg(bas, AR933X_UART_DATA_REG) & 0xff;
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/* Remove that entry from said RX FIFO */
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ar933x_setreg(bas, AR933X_UART_DATA_REG, AR933X_UART_DATA_RX_CSR);
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uart_unlock(hwmtx);
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return (c);
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}
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/*
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* High-level UART interface.
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*/
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struct ar933x_softc {
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struct uart_softc base;
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uint32_t u_ier;
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};
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static int ar933x_bus_attach(struct uart_softc *);
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static int ar933x_bus_detach(struct uart_softc *);
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static int ar933x_bus_flush(struct uart_softc *, int);
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static int ar933x_bus_getsig(struct uart_softc *);
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static int ar933x_bus_ioctl(struct uart_softc *, int, intptr_t);
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static int ar933x_bus_ipend(struct uart_softc *);
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static int ar933x_bus_param(struct uart_softc *, int, int, int, int);
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static int ar933x_bus_probe(struct uart_softc *);
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static int ar933x_bus_receive(struct uart_softc *);
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static int ar933x_bus_setsig(struct uart_softc *, int);
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static int ar933x_bus_transmit(struct uart_softc *);
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static void ar933x_bus_grab(struct uart_softc *);
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static void ar933x_bus_ungrab(struct uart_softc *);
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static kobj_method_t ar933x_methods[] = {
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KOBJMETHOD(uart_attach, ar933x_bus_attach),
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KOBJMETHOD(uart_detach, ar933x_bus_detach),
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KOBJMETHOD(uart_flush, ar933x_bus_flush),
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KOBJMETHOD(uart_getsig, ar933x_bus_getsig),
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KOBJMETHOD(uart_ioctl, ar933x_bus_ioctl),
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KOBJMETHOD(uart_ipend, ar933x_bus_ipend),
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KOBJMETHOD(uart_param, ar933x_bus_param),
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KOBJMETHOD(uart_probe, ar933x_bus_probe),
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KOBJMETHOD(uart_receive, ar933x_bus_receive),
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KOBJMETHOD(uart_setsig, ar933x_bus_setsig),
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KOBJMETHOD(uart_transmit, ar933x_bus_transmit),
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KOBJMETHOD(uart_grab, ar933x_bus_grab),
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KOBJMETHOD(uart_ungrab, ar933x_bus_ungrab),
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{ 0, 0 }
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};
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struct uart_class uart_ar933x_class = {
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"ar933x",
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ar933x_methods,
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sizeof(struct ar933x_softc),
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.uc_ops = &uart_ar933x_ops,
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.uc_range = 8,
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.uc_rclk = DEFAULT_RCLK
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};
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#define SIGCHG(c, i, s, d) \
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if (c) { \
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i |= (i & s) ? s : s | d; \
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} else { \
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i = (i & s) ? (i & ~s) | d : i; \
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}
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static int
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ar933x_bus_attach(struct uart_softc *sc)
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{
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struct ar933x_softc *u = (struct ar933x_softc *)sc;
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struct uart_bas *bas = &sc->sc_bas;
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uint32_t reg;
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|
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/* XXX TODO: flush transmitter */
|
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/*
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* Setup initial interrupt notifications.
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*
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* XXX for now, just RX FIFO valid.
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* Later on (when they're handled), also handle
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* RX errors/overflow.
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*/
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u->u_ier = AR933X_UART_INT_RX_VALID;
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/* Enable RX interrupts to kick-start things */
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ar933x_setreg(bas, AR933X_UART_INT_EN_REG, u->u_ier);
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/* Enable the host interrupt now */
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reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
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reg |= AR933X_UART_CS_HOST_INT_EN;
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ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
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return (0);
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}
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|
|
static int
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ar933x_bus_detach(struct uart_softc *sc)
|
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{
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struct uart_bas *bas = &sc->sc_bas;
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uint32_t reg;
|
|
|
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/* Disable all interrupts */
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ar933x_setreg(bas, AR933X_UART_INT_EN_REG, 0x00000000);
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|
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/* Disable the host interrupt */
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reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
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reg &= ~AR933X_UART_CS_HOST_INT_EN;
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ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
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uart_barrier(bas);
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|
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|
return (0);
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}
|
|
|
|
static int
|
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ar933x_bus_flush(struct uart_softc *sc, int what)
|
|
{
|
|
struct uart_bas *bas;
|
|
|
|
bas = &sc->sc_bas;
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uart_lock(sc->sc_hwmtx);
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ar933x_drain(bas, what);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ar933x_bus_getsig(struct uart_softc *sc)
|
|
{
|
|
uint32_t sig = sc->sc_hwsig;
|
|
|
|
/*
|
|
* For now, let's just return that DSR/DCD/CTS is asserted.
|
|
*/
|
|
SIGCHG(1, sig, SER_DSR, SER_DDSR);
|
|
SIGCHG(1, sig, SER_CTS, SER_DCTS);
|
|
SIGCHG(1, sig, SER_DCD, SER_DDCD);
|
|
SIGCHG(1, sig, SER_RI, SER_DRI);
|
|
|
|
sc->sc_hwsig = sig & ~SER_MASK_DELTA;
|
|
|
|
return (sig);
|
|
}
|
|
|
|
/*
|
|
* XXX TODO: actually implement the rest of this!
|
|
*/
|
|
static int
|
|
ar933x_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
|
|
{
|
|
int error = 0;
|
|
|
|
/* XXX lock */
|
|
switch (request) {
|
|
case UART_IOCTL_BREAK:
|
|
case UART_IOCTL_IFLOW:
|
|
case UART_IOCTL_OFLOW:
|
|
break;
|
|
case UART_IOCTL_BAUD:
|
|
*(int*)data = 115200;
|
|
break;
|
|
default:
|
|
error = EINVAL;
|
|
break;
|
|
}
|
|
|
|
/* XXX unlock */
|
|
|
|
return (error);
|
|
}
|
|
|
|
/*
|
|
* Bus interrupt handler.
|
|
*
|
|
* For now, system interrupts are disabled.
|
|
* So this is just called from a callout in uart_core.c
|
|
* to poll various state.
|
|
*/
|
|
static int
|
|
ar933x_bus_ipend(struct uart_softc *sc)
|
|
{
|
|
struct ar933x_softc *u = (struct ar933x_softc *)sc;
|
|
struct uart_bas *bas = &sc->sc_bas;
|
|
int ipend = 0;
|
|
uint32_t isr;
|
|
|
|
uart_lock(sc->sc_hwmtx);
|
|
|
|
/*
|
|
* Fetch/ACK the ISR status.
|
|
*/
|
|
isr = ar933x_getreg(bas, AR933X_UART_INT_REG);
|
|
ar933x_setreg(bas, AR933X_UART_INT_REG, isr);
|
|
uart_barrier(bas);
|
|
|
|
/*
|
|
* RX ready - notify upper layer.
|
|
*/
|
|
if (isr & AR933X_UART_INT_RX_VALID) {
|
|
ipend |= SER_INT_RXREADY;
|
|
}
|
|
|
|
/*
|
|
* If we get this interrupt, we should disable
|
|
* it from the interrupt mask and inform the uart
|
|
* driver appropriately.
|
|
*
|
|
* We can't keep setting SER_INT_TXIDLE or SER_INT_SIGCHG
|
|
* all the time or IO stops working. So we will always
|
|
* clear this interrupt if we get it, then we only signal
|
|
* the upper layer if we were doing active TX in the
|
|
* first place.
|
|
*
|
|
* Also, the name is misleading. This actually means
|
|
* "the FIFO is almost empty." So if we just write some
|
|
* more data to the FIFO without checking whether it can
|
|
* take said data, we'll overflow the thing.
|
|
*
|
|
* Unfortunately the FreeBSD uart device has no concept of
|
|
* partial UART writes - it expects that the whole buffer
|
|
* is written to the hardware. Thus for now, ar933x_bus_transmit()
|
|
* will wait for the FIFO to finish draining before it pushes
|
|
* more frames into it.
|
|
*/
|
|
if (isr & AR933X_UART_INT_TX_EMPTY) {
|
|
/*
|
|
* Update u_ier to disable TX notifications; update hardware
|
|
*/
|
|
u->u_ier &= ~AR933X_UART_INT_TX_EMPTY;
|
|
ar933x_setreg(bas, AR933X_UART_INT_EN_REG, u->u_ier);
|
|
uart_barrier(bas);
|
|
}
|
|
|
|
/*
|
|
* Only signal TX idle if we're not busy transmitting.
|
|
*
|
|
* XXX I never get _out_ of txbusy? Debug that!
|
|
*/
|
|
if (sc->sc_txbusy) {
|
|
if (isr & AR933X_UART_INT_TX_EMPTY) {
|
|
ipend |= SER_INT_TXIDLE;
|
|
} else {
|
|
ipend |= SER_INT_SIGCHG;
|
|
}
|
|
}
|
|
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (ipend);
|
|
}
|
|
|
|
static int
|
|
ar933x_bus_param(struct uart_softc *sc, int baudrate, int databits,
|
|
int stopbits, int parity)
|
|
{
|
|
struct uart_bas *bas;
|
|
int error;
|
|
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
error = ar933x_param(bas, baudrate, databits, stopbits, parity);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (error);
|
|
}
|
|
|
|
static int
|
|
ar933x_bus_probe(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas;
|
|
int error;
|
|
|
|
bas = &sc->sc_bas;
|
|
|
|
error = ar933x_probe(bas);
|
|
if (error)
|
|
return (error);
|
|
|
|
/* Reset FIFOs. */
|
|
ar933x_drain(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
|
|
|
|
/* XXX TODO: actually find out what the FIFO depth is! */
|
|
sc->sc_rxfifosz = 16;
|
|
sc->sc_txfifosz = 16;
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ar933x_bus_receive(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas = &sc->sc_bas;
|
|
int xc;
|
|
|
|
uart_lock(sc->sc_hwmtx);
|
|
|
|
/* Loop over until we are full, or no data is available */
|
|
while (ar933x_rxready(bas)) {
|
|
if (uart_rx_full(sc)) {
|
|
sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
|
|
break;
|
|
}
|
|
|
|
/* Read the top of the RX FIFO */
|
|
xc = ar933x_getreg(bas, AR933X_UART_DATA_REG) & 0xff;
|
|
|
|
/* Remove that entry from said RX FIFO */
|
|
ar933x_setreg(bas, AR933X_UART_DATA_REG,
|
|
AR933X_UART_DATA_RX_CSR);
|
|
uart_barrier(bas);
|
|
|
|
/* XXX frame, parity error */
|
|
uart_rx_put(sc, xc);
|
|
}
|
|
|
|
/*
|
|
* XXX TODO: Discard everything left in the Rx FIFO?
|
|
* XXX only if we've hit an overrun condition?
|
|
*/
|
|
|
|
uart_unlock(sc->sc_hwmtx);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ar933x_bus_setsig(struct uart_softc *sc, int sig)
|
|
{
|
|
#if 0
|
|
struct ar933x_softc *ns8250 = (struct ar933x_softc*)sc;
|
|
struct uart_bas *bas;
|
|
uint32_t new, old;
|
|
|
|
bas = &sc->sc_bas;
|
|
do {
|
|
old = sc->sc_hwsig;
|
|
new = old;
|
|
if (sig & SER_DDTR) {
|
|
SIGCHG(sig & SER_DTR, new, SER_DTR,
|
|
SER_DDTR);
|
|
}
|
|
if (sig & SER_DRTS) {
|
|
SIGCHG(sig & SER_RTS, new, SER_RTS,
|
|
SER_DRTS);
|
|
}
|
|
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
|
|
uart_lock(sc->sc_hwmtx);
|
|
ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
|
|
if (new & SER_DTR)
|
|
ns8250->mcr |= MCR_DTR;
|
|
if (new & SER_RTS)
|
|
ns8250->mcr |= MCR_RTS;
|
|
uart_setreg(bas, REG_MCR, ns8250->mcr);
|
|
uart_barrier(bas);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
#endif
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* Write the current transmit buffer to the TX FIFO.
|
|
*
|
|
* Unfortunately the FreeBSD uart device has no concept of
|
|
* partial UART writes - it expects that the whole buffer
|
|
* is written to the hardware. Thus for now, this will wait for
|
|
* the FIFO to finish draining before it pushes more frames into it.
|
|
*
|
|
* If non-blocking operation is truely needed here, either
|
|
* the FreeBSD uart device will need to handle partial writes
|
|
* in xxx_bus_transmit(), or we'll need to do TX FIFO buffering
|
|
* of our own here.
|
|
*/
|
|
static int
|
|
ar933x_bus_transmit(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas = &sc->sc_bas;
|
|
struct ar933x_softc *u = (struct ar933x_softc *)sc;
|
|
int i;
|
|
|
|
uart_lock(sc->sc_hwmtx);
|
|
|
|
/* Wait for the FIFO to be clear - see above */
|
|
while (ar933x_getreg(bas, AR933X_UART_CS_REG) &
|
|
AR933X_UART_CS_TX_BUSY)
|
|
;
|
|
|
|
/*
|
|
* Write some data!
|
|
*/
|
|
for (i = 0; i < sc->sc_txdatasz; i++) {
|
|
/* Write the TX data */
|
|
ar933x_setreg(bas, AR933X_UART_DATA_REG,
|
|
(sc->sc_txbuf[i] & 0xff) | AR933X_UART_DATA_TX_CSR);
|
|
uart_barrier(bas);
|
|
}
|
|
|
|
/*
|
|
* Now that we're transmitting, get interrupt notification
|
|
* when the FIFO is (almost) empty - see above.
|
|
*/
|
|
u->u_ier |= AR933X_UART_INT_TX_EMPTY;
|
|
ar933x_setreg(bas, AR933X_UART_INT_EN_REG, u->u_ier);
|
|
uart_barrier(bas);
|
|
|
|
/*
|
|
* Inform the upper layer that we are presently transmitting
|
|
* data to the hardware; this will be cleared when the
|
|
* TXIDLE interrupt occurs.
|
|
*/
|
|
sc->sc_txbusy = 1;
|
|
uart_unlock(sc->sc_hwmtx);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
ar933x_bus_grab(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas = &sc->sc_bas;
|
|
uint32_t reg;
|
|
|
|
/* Disable the host interrupt now */
|
|
uart_lock(sc->sc_hwmtx);
|
|
reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
|
|
reg &= ~AR933X_UART_CS_HOST_INT_EN;
|
|
ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
}
|
|
|
|
static void
|
|
ar933x_bus_ungrab(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas = &sc->sc_bas;
|
|
uint32_t reg;
|
|
|
|
/* Enable the host interrupt now */
|
|
uart_lock(sc->sc_hwmtx);
|
|
reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
|
|
reg |= AR933X_UART_CS_HOST_INT_EN;
|
|
ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
}
|